diff for duplicates of <4392776.GZArrLSWTI@diego> diff --git a/a/1.txt b/N1/1.txt index 39a50a6..355622b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -8,7 +8,7 @@ usb device and most likely from its emmc too, if the emmc uses a standard partition table instead of Rockchip's own one - the emmc itself is detected correctly. -Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> +Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- This of course needs the dt-binding header from clock series, so a shared branch will be needed. @@ -52,7 +52,7 @@ index 0000000..d0c519b +++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts @@ -0,0 +1,354 @@ +/* -+ * Copyright (c) 2015 Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> ++ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual @@ -123,7 +123,7 @@ index 0000000..d0c519b + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + -+ button@0 { ++ button at 0 { + gpio-key,wakeup = <1>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; @@ -267,7 +267,7 @@ index 0000000..d0c519b +&i2c0 { + status = "okay"; + -+ vdd_cpu: syr827@40 { ++ vdd_cpu: syr827 at 40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; @@ -281,7 +281,7 @@ index 0000000..d0c519b + vin-supply = <&vcc_sys>; + }; + -+ hym8563: hym8563@51 { ++ hym8563: hym8563 at 51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; @@ -412,7 +412,7 @@ index 0000000..a712bea +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -0,0 +1,900 @@ +/* -+ * Copyright (c) 2015 Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> ++ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual @@ -530,7 +530,7 @@ index 0000000..a712bea + }; + }; + -+ cpu_l0: cpu@0 { ++ cpu_l0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; @@ -538,7 +538,7 @@ index 0000000..a712bea + enable-method = "psci"; + }; + -+ cpu_l1: cpu@1 { ++ cpu_l1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; @@ -546,7 +546,7 @@ index 0000000..a712bea + enable-method = "psci"; + }; + -+ cpu_l2: cpu@2 { ++ cpu_l2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; @@ -554,7 +554,7 @@ index 0000000..a712bea + enable-method = "psci"; + }; + -+ cpu_l3: cpu@3 { ++ cpu_l3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; @@ -562,7 +562,7 @@ index 0000000..a712bea + enable-method = "psci"; + }; + -+ cpu_b0: cpu@100 { ++ cpu_b0: cpu at 100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x100>; @@ -570,7 +570,7 @@ index 0000000..a712bea + enable-method = "psci"; + }; + -+ cpu_b1: cpu@101 { ++ cpu_b1: cpu at 101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x101>; @@ -578,7 +578,7 @@ index 0000000..a712bea + enable-method = "psci"; + }; + -+ cpu_b2: cpu@102 { ++ cpu_b2: cpu at 102 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x102>; @@ -586,7 +586,7 @@ index 0000000..a712bea + enable-method = "psci"; + }; + -+ cpu_b3: cpu@103 { ++ cpu_b3: cpu at 103 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x103>; @@ -634,7 +634,7 @@ index 0000000..a712bea + #clock-cells = <0>; + }; + -+ sdmmc: dwmmc@ff0c0000 { ++ sdmmc: dwmmc at ff0c0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0c0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; @@ -645,7 +645,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ sdio0: dwmmc@ff0d0000 { ++ sdio0: dwmmc at ff0d0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0d0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; @@ -657,7 +657,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ emmc: dwmmc@ff0f0000 { ++ emmc: dwmmc at ff0f0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0f0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; @@ -668,7 +668,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ saradc: saradc@ff100000 { ++ saradc: saradc at ff100000 { + compatible = "rockchip,saradc"; + reg = <0x0 0xff100000 0x0 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; @@ -678,7 +678,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ spi0: spi@ff110000 { ++ spi0: spi at ff110000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff110000 0x0 0x1000>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; @@ -691,7 +691,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ spi1: spi@ff120000 { ++ spi1: spi at ff120000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff120000 0x0 0x1000>; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; @@ -704,7 +704,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ spi2: spi@ff130000 { ++ spi2: spi at ff130000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff130000 0x0 0x1000>; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; @@ -717,7 +717,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ i2c1: i2c@ff140000 { ++ i2c1: i2c at ff140000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff140000 0x0 0x1000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; @@ -730,7 +730,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ i2c3: i2c@ff150000 { ++ i2c3: i2c at ff150000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; @@ -743,7 +743,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ i2c4: i2c@ff160000 { ++ i2c4: i2c at ff160000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; @@ -756,7 +756,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ i2c5: i2c@ff170000 { ++ i2c5: i2c at ff170000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff170000 0x0 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; @@ -769,7 +769,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ uart0: serial@ff180000 { ++ uart0: serial at ff180000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + clock-frequency = <24000000>; @@ -781,7 +781,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ uart1: serial@ff190000 { ++ uart1: serial at ff190000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff190000 0x0 0x100>; + clock-frequency = <24000000>; @@ -793,7 +793,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ uart3: serial@ff1b0000 { ++ uart3: serial at ff1b0000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1b0000 0x0 0x100>; + clock-frequency = <24000000>; @@ -805,7 +805,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ uart4: serial@ff1c0000 { ++ uart4: serial at ff1c0000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1c0000 0x0 0x100>; + clock-frequency = <24000000>; @@ -817,7 +817,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ gmac: ethernet@ff290000 { ++ gmac: ethernet at ff290000 { + compatible = "rockchip,rk3368-gmac"; + reg = <0x0 0xff290000 0x0 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; @@ -834,7 +834,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ usb_host0_ehci: usb@ff500000 { ++ usb_host0_ehci: usb at ff500000 { + compatible = "generic-ehci"; + reg = <0x0 0xff500000 0x0 0x100>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; @@ -843,7 +843,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ usb_otg: usb@ff580000 { ++ usb_otg: usb at ff580000 { + compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff580000 0x0 0x40000>; @@ -858,7 +858,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ i2c0: i2c@ff650000 { ++ i2c0: i2c at ff650000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff650000 0x0 0x1000>; + clocks = <&cru PCLK_I2C0>; @@ -871,7 +871,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ i2c2: i2c@ff660000 { ++ i2c2: i2c at ff660000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff660000 0x0 0x1000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; @@ -884,7 +884,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ uart2: serial@ff690000 { ++ uart2: serial at ff690000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff690000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; @@ -897,12 +897,12 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ pmugrf: syscon@ff738000 { ++ pmugrf: syscon at ff738000 { + compatible = "rockchip,rk3368-pmugrf", "syscon"; + reg = <0x0 0xff738000 0x0 0x1000>; + }; + -+ cru: clock-controller@ff760000 { ++ cru: clock-controller at ff760000 { + compatible = "rockchip,rk3368-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + rockchip,grf = <&grf>; @@ -910,12 +910,12 @@ index 0000000..a712bea + #reset-cells = <1>; + }; + -+ grf: syscon@ff770000 { ++ grf: syscon at ff770000 { + compatible = "rockchip,rk3368-grf", "syscon"; + reg = <0x0 0xff770000 0x0 0x1000>; + }; + -+ wdt: watchdog@ff800000 { ++ wdt: watchdog at ff800000 { + compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; + reg = <0x0 0xff800000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; @@ -923,7 +923,7 @@ index 0000000..a712bea + status = "disabled"; + }; + -+ gic: interrupt-controller@ffb71000 { ++ gic: interrupt-controller at ffb71000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; @@ -945,7 +945,7 @@ index 0000000..a712bea + #size-cells = <0x2>; + ranges; + -+ gpio0: gpio0@ff750000 { ++ gpio0: gpio0 at ff750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff750000 0x0 0x100>; + clocks = <&cru PCLK_GPIO0>; @@ -958,7 +958,7 @@ index 0000000..a712bea + #interrupt-cells = <0x2>; + }; + -+ gpio1: gpio1@ff780000 { ++ gpio1: gpio1 at ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff780000 0x0 0x100>; + clocks = <&cru PCLK_GPIO1>; @@ -971,7 +971,7 @@ index 0000000..a712bea + #interrupt-cells = <0x2>; + }; + -+ gpio2: gpio2@ff790000 { ++ gpio2: gpio2 at ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff790000 0x0 0x100>; + clocks = <&cru PCLK_GPIO2>; @@ -984,7 +984,7 @@ index 0000000..a712bea + #interrupt-cells = <0x2>; + }; + -+ gpio3: gpio3@ff7a0000 { ++ gpio3: gpio3 at ff7a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff7a0000 0x0 0x100>; + clocks = <&cru PCLK_GPIO3>; @@ -1313,9 +1313,3 @@ index 0000000..a712bea +}; -- 2.1.4 - - --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 994f057..91c38a0 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,8 @@ "ref\03333434.ZKWQ6GxgtB@diego\0" - "From\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" + "From\0heiko@sntech.de (Heiko St\303\274bner)\0" "Subject\0[PATCH v2 3/4] arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board\0" "Date\0Mon, 29 Jun 2015 14:34:35 +0200\0" - "To\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" - "Cc\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>" - Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> - Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> - Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> - Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> - Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> - Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - " linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "In terms of peripherals the rk3368 is quite similar to the rk3288, which\n" @@ -24,7 +15,7 @@ "partition table instead of Rockchip's own one - the emmc itself is\n" "detected correctly.\n" "\n" - "Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "Signed-off-by: Heiko Stuebner <heiko@sntech.de>\n" "---\n" "This of course needs the dt-binding header from clock series, so\n" "a shared branch will be needed.\n" @@ -68,7 +59,7 @@ "+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts\n" "@@ -0,0 +1,354 @@\n" "+/*\n" - "+ * Copyright (c) 2015 Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "+ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>\n" "+ *\n" "+ * This file is dual-licensed: you can use it either under the terms\n" "+ * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -139,7 +130,7 @@ "+\t\tpinctrl-names = \"default\";\n" "+\t\tpinctrl-0 = <&pwr_key>;\n" "+\n" - "+\t\tbutton@0 {\n" + "+\t\tbutton at 0 {\n" "+\t\t\tgpio-key,wakeup = <1>;\n" "+\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n" "+\t\t\tlabel = \"GPIO Power\";\n" @@ -283,7 +274,7 @@ "+&i2c0 {\n" "+\tstatus = \"okay\";\n" "+\n" - "+\tvdd_cpu: syr827@40 {\n" + "+\tvdd_cpu: syr827 at 40 {\n" "+\t\tcompatible = \"silergy,syr827\";\n" "+\t\treg = <0x40>;\n" "+\t\tfcs,suspend-voltage-selector = <1>;\n" @@ -297,7 +288,7 @@ "+\t\tvin-supply = <&vcc_sys>;\n" "+\t};\n" "+\n" - "+\thym8563: hym8563@51 {\n" + "+\thym8563: hym8563 at 51 {\n" "+\t\tcompatible = \"haoyu,hym8563\";\n" "+\t\treg = <0x51>;\n" "+\t\t#clock-cells = <0>;\n" @@ -428,7 +419,7 @@ "+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi\n" "@@ -0,0 +1,900 @@\n" "+/*\n" - "+ * Copyright (c) 2015 Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "+ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>\n" "+ *\n" "+ * This file is dual-licensed: you can use it either under the terms\n" "+ * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -546,7 +537,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tcpu_l0: cpu@0 {\n" + "+\t\tcpu_l0: cpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x0>;\n" @@ -554,7 +545,7 @@ "+\t\t\tenable-method = \"psci\";\n" "+\t\t};\n" "+\n" - "+\t\tcpu_l1: cpu@1 {\n" + "+\t\tcpu_l1: cpu at 1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x1>;\n" @@ -562,7 +553,7 @@ "+\t\t\tenable-method = \"psci\";\n" "+\t\t};\n" "+\n" - "+\t\tcpu_l2: cpu@2 {\n" + "+\t\tcpu_l2: cpu at 2 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x2>;\n" @@ -570,7 +561,7 @@ "+\t\t\tenable-method = \"psci\";\n" "+\t\t};\n" "+\n" - "+\t\tcpu_l3: cpu@3 {\n" + "+\t\tcpu_l3: cpu at 3 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x3>;\n" @@ -578,7 +569,7 @@ "+\t\t\tenable-method = \"psci\";\n" "+\t\t};\n" "+\n" - "+\t\tcpu_b0: cpu@100 {\n" + "+\t\tcpu_b0: cpu at 100 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x100>;\n" @@ -586,7 +577,7 @@ "+\t\t\tenable-method = \"psci\";\n" "+\t\t};\n" "+\n" - "+\t\tcpu_b1: cpu@101 {\n" + "+\t\tcpu_b1: cpu at 101 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x101>;\n" @@ -594,7 +585,7 @@ "+\t\t\tenable-method = \"psci\";\n" "+\t\t};\n" "+\n" - "+\t\tcpu_b2: cpu@102 {\n" + "+\t\tcpu_b2: cpu at 102 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x102>;\n" @@ -602,7 +593,7 @@ "+\t\t\tenable-method = \"psci\";\n" "+\t\t};\n" "+\n" - "+\t\tcpu_b3: cpu@103 {\n" + "+\t\tcpu_b3: cpu at 103 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x103>;\n" @@ -650,7 +641,7 @@ "+\t\t#clock-cells = <0>;\n" "+\t};\n" "+\n" - "+\tsdmmc: dwmmc@ff0c0000 {\n" + "+\tsdmmc: dwmmc at ff0c0000 {\n" "+\t\tcompatible = \"rockchip,rk3368-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n" "+\t\treg = <0x0 0xff0c0000 0x0 0x4000>;\n" "+\t\tclock-freq-min-max = <400000 150000000>;\n" @@ -661,7 +652,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tsdio0: dwmmc@ff0d0000 {\n" + "+\tsdio0: dwmmc at ff0d0000 {\n" "+\t\tcompatible = \"rockchip,rk3368-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n" "+\t\treg = <0x0 0xff0d0000 0x0 0x4000>;\n" "+\t\tclock-freq-min-max = <400000 150000000>;\n" @@ -673,7 +664,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\temmc: dwmmc@ff0f0000 {\n" + "+\temmc: dwmmc at ff0f0000 {\n" "+\t\tcompatible = \"rockchip,rk3368-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n" "+\t\treg = <0x0 0xff0f0000 0x0 0x4000>;\n" "+\t\tclock-freq-min-max = <400000 150000000>;\n" @@ -684,7 +675,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tsaradc: saradc@ff100000 {\n" + "+\tsaradc: saradc at ff100000 {\n" "+\t\tcompatible = \"rockchip,saradc\";\n" "+\t\treg = <0x0 0xff100000 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -694,7 +685,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tspi0: spi@ff110000 {\n" + "+\tspi0: spi at ff110000 {\n" "+\t\tcompatible = \"rockchip,rk3368-spi\", \"rockchip,rk3066-spi\";\n" "+\t\treg = <0x0 0xff110000 0x0 0x1000>;\n" "+\t\tclocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;\n" @@ -707,7 +698,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tspi1: spi@ff120000 {\n" + "+\tspi1: spi at ff120000 {\n" "+\t\tcompatible = \"rockchip,rk3368-spi\", \"rockchip,rk3066-spi\";\n" "+\t\treg = <0x0 0xff120000 0x0 0x1000>;\n" "+\t\tclocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;\n" @@ -720,7 +711,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tspi2: spi@ff130000 {\n" + "+\tspi2: spi at ff130000 {\n" "+\t\tcompatible = \"rockchip,rk3368-spi\", \"rockchip,rk3066-spi\";\n" "+\t\treg = <0x0 0xff130000 0x0 0x1000>;\n" "+\t\tclocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;\n" @@ -733,7 +724,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c1: i2c@ff140000 {\n" + "+\ti2c1: i2c at ff140000 {\n" "+\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0x0 0xff140000 0x0 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -746,7 +737,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c3: i2c@ff150000 {\n" + "+\ti2c3: i2c at ff150000 {\n" "+\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0x0 0xff150000 0x0 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -759,7 +750,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c4: i2c@ff160000 {\n" + "+\ti2c4: i2c at ff160000 {\n" "+\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0x0 0xff160000 0x0 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -772,7 +763,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c5: i2c@ff170000 {\n" + "+\ti2c5: i2c at ff170000 {\n" "+\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0x0 0xff170000 0x0 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -785,7 +776,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart0: serial@ff180000 {\n" + "+\tuart0: serial at ff180000 {\n" "+\t\tcompatible = \"rockchip,rk3368-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff180000 0x0 0x100>;\n" "+\t\tclock-frequency = <24000000>;\n" @@ -797,7 +788,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart1: serial@ff190000 {\n" + "+\tuart1: serial at ff190000 {\n" "+\t\tcompatible = \"rockchip,rk3368-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff190000 0x0 0x100>;\n" "+\t\tclock-frequency = <24000000>;\n" @@ -809,7 +800,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart3: serial@ff1b0000 {\n" + "+\tuart3: serial at ff1b0000 {\n" "+\t\tcompatible = \"rockchip,rk3368-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff1b0000 0x0 0x100>;\n" "+\t\tclock-frequency = <24000000>;\n" @@ -821,7 +812,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart4: serial@ff1c0000 {\n" + "+\tuart4: serial at ff1c0000 {\n" "+\t\tcompatible = \"rockchip,rk3368-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff1c0000 0x0 0x100>;\n" "+\t\tclock-frequency = <24000000>;\n" @@ -833,7 +824,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tgmac: ethernet@ff290000 {\n" + "+\tgmac: ethernet at ff290000 {\n" "+\t\tcompatible = \"rockchip,rk3368-gmac\";\n" "+\t\treg = <0x0 0xff290000 0x0 0x10000>;\n" "+\t\tinterrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -850,7 +841,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tusb_host0_ehci: usb@ff500000 {\n" + "+\tusb_host0_ehci: usb at ff500000 {\n" "+\t\tcompatible = \"generic-ehci\";\n" "+\t\treg = <0x0 0xff500000 0x0 0x100>;\n" "+\t\tinterrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -859,7 +850,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tusb_otg: usb@ff580000 {\n" + "+\tusb_otg: usb at ff580000 {\n" "+\t\tcompatible = \"rockchip,rk3368-usb\", \"rockchip,rk3066-usb\",\n" "+\t\t\t\t\"snps,dwc2\";\n" "+\t\treg = <0x0 0xff580000 0x0 0x40000>;\n" @@ -874,7 +865,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c0: i2c@ff650000 {\n" + "+\ti2c0: i2c at ff650000 {\n" "+\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0x0 0xff650000 0x0 0x1000>;\n" "+\t\tclocks = <&cru PCLK_I2C0>;\n" @@ -887,7 +878,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\ti2c2: i2c@ff660000 {\n" + "+\ti2c2: i2c at ff660000 {\n" "+\t\tcompatible = \"rockchip,rk3368-i2c\", \"rockchip,rk3288-i2c\";\n" "+\t\treg = <0x0 0xff660000 0x0 0x1000>;\n" "+\t\tinterrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -900,7 +891,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tuart2: serial@ff690000 {\n" + "+\tuart2: serial at ff690000 {\n" "+\t\tcompatible = \"rockchip,rk3368-uart\", \"snps,dw-apb-uart\";\n" "+\t\treg = <0x0 0xff690000 0x0 0x100>;\n" "+\t\tclocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;\n" @@ -913,12 +904,12 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tpmugrf: syscon@ff738000 {\n" + "+\tpmugrf: syscon at ff738000 {\n" "+\t\tcompatible = \"rockchip,rk3368-pmugrf\", \"syscon\";\n" "+\t\treg = <0x0 0xff738000 0x0 0x1000>;\n" "+\t};\n" "+\n" - "+\tcru: clock-controller@ff760000 {\n" + "+\tcru: clock-controller at ff760000 {\n" "+\t\tcompatible = \"rockchip,rk3368-cru\";\n" "+\t\treg = <0x0 0xff760000 0x0 0x1000>;\n" "+\t\trockchip,grf = <&grf>;\n" @@ -926,12 +917,12 @@ "+\t\t#reset-cells = <1>;\n" "+\t};\n" "+\n" - "+\tgrf: syscon@ff770000 {\n" + "+\tgrf: syscon at ff770000 {\n" "+\t\tcompatible = \"rockchip,rk3368-grf\", \"syscon\";\n" "+\t\treg = <0x0 0xff770000 0x0 0x1000>;\n" "+\t};\n" "+\n" - "+\twdt: watchdog@ff800000 {\n" + "+\twdt: watchdog at ff800000 {\n" "+\t\tcompatible = \"rockchip,rk3368-wdt\", \"snps,dw-wdt\";\n" "+\t\treg = <0x0 0xff800000 0x0 0x100>;\n" "+\t\tclocks = <&cru PCLK_WDT>;\n" @@ -939,7 +930,7 @@ "+\t\tstatus = \"disabled\";\n" "+\t};\n" "+\n" - "+\tgic: interrupt-controller@ffb71000 {\n" + "+\tgic: interrupt-controller at ffb71000 {\n" "+\t\tcompatible = \"arm,gic-400\";\n" "+\t\tinterrupt-controller;\n" "+\t\t#interrupt-cells = <3>;\n" @@ -961,7 +952,7 @@ "+\t\t#size-cells = <0x2>;\n" "+\t\tranges;\n" "+\n" - "+\t\tgpio0: gpio0@ff750000 {\n" + "+\t\tgpio0: gpio0 at ff750000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0x0 0xff750000 0x0 0x100>;\n" "+\t\t\tclocks = <&cru PCLK_GPIO0>;\n" @@ -974,7 +965,7 @@ "+\t\t\t#interrupt-cells = <0x2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio1: gpio1@ff780000 {\n" + "+\t\tgpio1: gpio1 at ff780000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0x0 0xff780000 0x0 0x100>;\n" "+\t\t\tclocks = <&cru PCLK_GPIO1>;\n" @@ -987,7 +978,7 @@ "+\t\t\t#interrupt-cells = <0x2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio2: gpio2@ff790000 {\n" + "+\t\tgpio2: gpio2 at ff790000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0x0 0xff790000 0x0 0x100>;\n" "+\t\t\tclocks = <&cru PCLK_GPIO2>;\n" @@ -1000,7 +991,7 @@ "+\t\t\t#interrupt-cells = <0x2>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio3: gpio3@ff7a0000 {\n" + "+\t\tgpio3: gpio3 at ff7a0000 {\n" "+\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\treg = <0x0 0xff7a0000 0x0 0x100>;\n" "+\t\t\tclocks = <&cru PCLK_GPIO3>;\n" @@ -1328,12 +1319,6 @@ "+\t};\n" "+};\n" "-- \n" - "2.1.4\n" - "\n" - "\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + 2.1.4 -26a02a2ca9675a20cac2f383bc01e6c89b0b4f3936980693e801320daa2b604f +90c4a151efc493d6a6acccc378f0fb15dbdeccb57a8a6d1217c079ffe0ab183a
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