From: Bernhard Priewasser <priewasser@gmail.com>
To: Jared Hulbert <jaredeh@gmail.com>
Cc: MTD mailing list <linux-mtd@lists.infradead.org>
Subject: Re: Strange NOR read/write throughput behaviour
Date: Tue, 06 Dec 2005 13:14:34 +0100 [thread overview]
Message-ID: <439580AA.4050407@gmail.com> (raw)
In-Reply-To: <6934efce0512031336p292fd27fjbfbf6fbabd750023@mail.gmail.com>
> Sorry for the long wait.
No problem.
> Let me ask around a little more. This is an arm7 processor,
> no L1 or L2 caches?
ARM 720T, 8 KiB combined instruction/data cache. I don't know if there
is any L2-Cache on Hynix HMS30C7202; but if there is one, I doubt it's
as big as 128 KiB.
It looks pretty much like there is a cache sized 128 KiB somewhere
beetween fread() and the flash. But don't know where...
--
Bernhard
prev parent reply other threads:[~2005-12-06 12:14 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-11-15 10:27 Strange NOR read/write throughput behaviour Bernhard Priewasser
2005-11-17 17:58 ` Jared Hulbert
2005-11-18 9:31 ` Bernhard Priewasser
2005-11-21 22:18 ` Jared Hulbert
2005-11-22 10:14 ` Bernhard Priewasser
2005-12-03 21:36 ` Jared Hulbert
2005-12-06 12:14 ` Bernhard Priewasser [this message]
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