[PATCH]fix clts issue for vmx guest

["Ling, Xiaofeng" <xiaofeng.ling@intel.com>]

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# HG changeset patch
# User Xiaofeng Ling <xiaofeng.ling@intel.com>
# Node ID c137bd19e407f249d22784884e6a8f31154bee82
# Parent  179f7d89d368511f6eaaf870fcc580c02c838916
Fix the issue when guest OS clear TS bit by mov to cr0 instead of
clts instruction for floating point context save and restore.
clts instruction is already handled in vmx exit handler while
vmx_set_cr0 has not handled it yet.

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# HG changeset patch
# User Xiaofeng Ling <xiaofeng.ling@intel.com>
# Node ID c137bd19e407f249d22784884e6a8f31154bee82
# Parent  179f7d89d368511f6eaaf870fcc580c02c838916
Fix the issue when guest OS clear TS bit by mov to cr0 instead of 
clts instruction for floating point context save and restore.
clts instruction is already handled in vmx exit handler while 
vmx_set_cr0 has not handled it yet.

Signed-off-by: Xiaofeng Ling <xiaofeng.ling@intel.com>

diff -r 179f7d89d368 -r c137bd19e407 xen/arch/x86/vmx.c
--- a/xen/arch/x86/vmx.c	Wed Dec 14 12:45:26 2005 +0800
+++ b/xen/arch/x86/vmx.c	Wed Dec 14 13:06:39 2005 +0800
@@ -1109,11 +1109,21 @@
     unsigned long eip;
     int paging_enabled;
     unsigned long vm_entry_value;
+    unsigned long old_cr0;
 
     /*
      * CR0: We don't want to lose PE and PG.
      */
-    paging_enabled = vmx_paging_enabled(v);
+    __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
+    paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
+    /* If OS don't use clts to clear TS bit...*/
+    if((old_cr0 & X86_CR0_TS) && !(value & X86_CR0_TS))
+    {
+            clts();
+            setup_fpu(v);
+    }
+
+
     __vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
     __vmwrite(CR0_READ_SHADOW, value);
 

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