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Sun, 25 Feb 2024 02:16:40 -0800 (PST) Message-ID: <439bbdad-ad63-4975-968a-e050564f002e@ventanamicro.com> Date: Sun, 25 Feb 2024 07:16:36 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] target/riscv: Fix shift count overflow To: "demin.han" , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20240225032720.375078-1-demin.han@starfivetech.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20240225032720.375078-1-demin.han@starfivetech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 2/25/24 00:27, demin.han wrote: > The result of (8 - 3 - vlmul) is negtive when vlmul >= 6, > and results in wrong vill. > > Signed-off-by: demin.han > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/vector_helper.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 84cec73eb2..fe56c007d5 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -44,6 +44,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > target_ulong reserved = s2 & > MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, > xlen - 1 - R_VTYPE_RESERVED_SHIFT); > + uint16_t vlen = cpu->cfg.vlenb << 3; > int8_t lmul; > > if (vlmul & 4) { > @@ -53,10 +54,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > * VLEN * LMUL >= SEW > * VLEN >> (8 - lmul) >= sew > * (vlenb << 3) >> (8 - lmul) >= sew > - * vlenb >> (8 - 3 - lmul) >= sew > */ > - if (vlmul == 4 || > - cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) { > + if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) { > vill = true; > } > }