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From: Philippe Gerum <rpm@xenomai.org>
To: ROSSIER Daniel <Daniel.Rossier@domain.hid>
Cc: xenomai@xenomai.org
Subject: Re: [Xenomai-core] Timer and calibration
Date: Tue, 21 Feb 2006 12:41:01 +0100	[thread overview]
Message-ID: <43FAFC4D.8070709@domain.hid> (raw)
In-Reply-To: <FDBBB5CC70676540B3EF7CFE83FD94E0210D24@domain.hid>

ROSSIER Daniel wrote:
> Hello,
> 
>  
> 
> We are currently porting Adeos/Xenomai with Linux 2.6.14 on a ARM9-based 
> Freescale i.mx21 (litekit) development board.
> 
> We started from the available patch for the ARM-based Integrator board.
> 
>  
> 
> We are now facing some interesting problems regarding clock/timer 
> frequencies with this board, but they are about to be solved J
> 
>  
> 
> However, we have a question of understanding; as far as we know, ipipe 
> starts with an aperiodic (one-shot) timer at the initialization time, 
> and that before
> 
> the calibrate function has been called. So, we get one interrupt only 
> since the xenomai scheduler has not been registered (we understand
> 
> that the xenomai scheduler should give the next timer shot, but since it 
> is not registered yet, no timer reprogramming is achieved).
> 
>  
> 
> So, how can the calibrate function can be invoked safely if no timer IRQ 
> is received since this kind of calibration comes before the xenomai 
> registration
> 
> (the calibrate function needs IRQ timers to calibrate the number of busy 
> loops between two jiffies) ?
> 

Unlike Linux's calibrate_delay loop, Xenomai's timer calibration code does not 
measure the CPU performance level, but only the average cost of programming the 
underlying timer hw in oneshot mode (time-wise), so that the nucleus can take this 
unavoidable delay into account when programming the next shot.

Nowadays, this is basically an x86+8254 PIT only issue, since on this platform, 
one has to go through the ISA bus to (re)program the PIT for the next timer shot, 
and this is quite expensive (1.5 - 2.5 us for each outb, and you need two of them 
for programming the shot). Btw, this is the reason why using the APIC when 
available on x86 is always a good idea, since it only costs ~100 ns to program the 
timer there through a memory mapped register.

IOW, the code does not wait for any timer IRQ, but only measures the average time 
for setting up the proper hw registers in order to program a timer shot.

>  
> 
> How is it realized with a x86 architecture (another timer source?)
> 

Look at ksrc/arch/*/hal.c, where all archs implement rthal_timer_calibrate() their 
own way.

>  
> 
> Is there any documentation – or discussion threads - which gives some 
> information about the use of timers/RTC/TSC with Xenomai?
> 

Maybe. Try browsing the archive.

>  
> 
> Thanks so much for your help
> 
>  
> 
> Kind regards
> 
>  
> 
> Daniel Rossier
> 
> 
> ------------------------------------------------------------------------
> 
> _______________________________________________
> Xenomai-core mailing list
> Xenomai-core@domain.hid
> https://mail.gna.org/listinfo/xenomai-core


-- 

Philippe.


  reply	other threads:[~2006-02-21 11:41 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-02-21 10:57 [Xenomai-core] Timer and calibration ROSSIER Daniel
2006-02-21 11:41 ` Philippe Gerum [this message]
     [not found] <FDBBB5CC70676540B3EF7CFE83FD94E0210D26@domain.hid>
     [not found] ` <43FB003B.1090409@domain.hid>
2006-02-21 13:34   ` ROSSIER Daniel
2006-02-21 14:12     ` Philippe Gerum

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