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[213.161.3.76]) by smtp.gmail.com with ESMTPSA id f6-20020a05600c4e8600b0039466988f6csm3062560wmq.31.2022.05.31.08.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 08:22:47 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Linus Walleij , Chen-Yu Tsai , Samuel Holland Cc: Andre Przywara , Maxime Ripard , Samuel Holland , Krzysztof Kozlowski , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH 0/3] pinctrl: sunxi: Remove non-existent reset line references Date: Tue, 31 May 2022 17:22:46 +0200 Message-ID: <4400164.LvFx2qVVIh@kista> In-Reply-To: <20220531053623.43851-1-samuel@sholland.org> References: <20220531053623.43851-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Dne torek, 31. maj 2022 ob 07:36:20 CEST je Samuel Holland napisal(a): > I assume these properties came from a lack of documentation, and the > very reasonable assumption that where there's a clock gate bit in the > CCU, there's a reset bit. But the pin controllers are special and don't > have a module reset line. The only way to reset the pin controller is to > reset the whole VDD_SYS power domain. > > This series is preparation for converting the PRCM MFD and legacy clock > drivers to a CCU clock/reset driver like all of the other Allwinner > SoCs. I don't plan to add reset lines that don't actually exist to the > new CCU driver. So we might as well get rid of the references now. > Technically this breaks devicetree compatibility, since the old drivers > expect the reset. But the CCU conversion will be a compatibility break > anyway, so it's a bit of a moot point. If I understand correclty, this would cause only DT forward compatibility issue, which happens now and then anyway. Kernel would still be compatible with older DTs, it would just ignore that reset, right? Best regards, Jernej > > > Samuel Holland (3): > pinctrl: sunxi: Remove reset controller consumers > ARM: dts: sunxi: Drop resets from r_pio nodes > dt-bindings: pinctrl: sunxi: Disallow the resets property > > .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 3 --- > arch/arm/boot/dts/sun6i-a31.dtsi | 1 - > arch/arm/boot/dts/sun8i-a23-a33.dtsi | 1 - > arch/arm/boot/dts/sun9i-a80.dtsi | 1 - > drivers/pinctrl/sunxi/Kconfig | 3 --- > drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 1 - > drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 1 - > drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c | 1 - > drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 22 +--------------- > drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 25 +------------------ > drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c | 1 - > drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c | 1 - > 12 files changed, 2 insertions(+), 59 deletions(-) > > -- > 2.35.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52FAAC433EF for ; Tue, 31 May 2022 15:24:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nOKhnLJsF3aXS0iZTNSHgQMgXKrGbjWHooCWwBjfuV4=; b=MDDdzccxaeeSgV gUNnsDRdSED8ufFnhy4jGV/9ozXWQaAPtPOXrxqfXSDRdqcdwxIJPSKPM/hCRGIkQJCpLxQOtGKYb 7aNhBufsZdSUCrZDOAh37GpvxhKImTHpW3lkYkLFhHyX+IU5XSymyrE5dyC1rRxM2ZaVagjNNgmYw eEQO9QcafYDldQeMsVTxA9Lpmt/z01HWDQv+yDF70iezR7FgKQM/ULcqU2fax0XsiI0BXyYbvjVEE rmhe8HcvaW02mr+k2a79dnhL8zY6dTgLfmC+zP+8PZdX8ROP9W13MJenFdZVJRTKY2a1IC8JSDqTn wSTuNwDz4baXRtUiyACA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nw3hw-00BXFG-H0; Tue, 31 May 2022 15:22:56 +0000 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nw3hs-00BXDz-JC for linux-arm-kernel@lists.infradead.org; Tue, 31 May 2022 15:22:54 +0000 Received: by mail-wr1-x434.google.com with SMTP id u3so19159582wrg.3 for ; Tue, 31 May 2022 08:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8dhNZzxcDqH8eUH1s8IHbudWKgs58nSE0muzeXBTjuY=; b=E1GQjuZW9sZHmfYcFMJ1aCOAduFcwcvyblhlBvq/cAFNzFuTn0SKU0mRpFpAYYq4M4 RL7F92BzzyAnPM+7e4UY7ciMPz1wi0xQ5Niwo428c0HGjrqIg5PgayxupDIiTTJufuT/ yavaeCJzEc7NIym5JQLqM5AFLnckZMuEBgZ4JW7vgmEHVAZ5m6gAwzKykayGuJYLM/tN s3qc8N1ZX3AwBYay53ph+wJtHECS7/3YjHhRx7xzCPST8JPg9AqSJIJql0Cw+8t2+9ec Qf3f4nFLfrNlYYK/JGoZXuS8zAk3wFPqBj5EaAB9zJWye79Ru3uliTiU49n2NCFr6Ybo rmxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8dhNZzxcDqH8eUH1s8IHbudWKgs58nSE0muzeXBTjuY=; b=DzFVIkNaBv3wUmuX+EZ+W8vqk8u1/ktYUnl7MpD2fscmB3HISpEpN0FSG1DeB6CSjS 0rx0cS1ZQqakbWwhrbmZcAwt6EICi9elTriCbEsy29iyiaAmMYTwwEjkzkHPJz1rG0CU U64teozrCAnd1DXi1VHy+1FX5A+Z16QOCFWruH0X/oaiL1k/cAew5lgub0vxmilKftxo 6GmrgR3x9hjcOywb1dz1bDpUCmSgqXzd0gSKF/KhHiXLw774AfZ0HbTXR3yLIdhE/qgI NQ92VwtaYcVgiui4wesjjQ+UcRwvQaRVs4Ys7NBMTlZ2ziNor19dg3UmVNOxxONlPW1J yicg== X-Gm-Message-State: AOAM531jGUuwa1C8Lpu6F51iPNNSuDuQxIWGpjPy3C8GwM6yKTfQABDD PTyIb3uTQ0Dij9lqP4XBJSg= X-Google-Smtp-Source: ABdhPJzxQR5NMIK+rbklutVxfOhZ8bGcR/zgUdGkNetM8QcimtFO8AwzM70tocDrq5+3XsEckuxvww== X-Received: by 2002:a5d:54c3:0:b0:210:2a28:5666 with SMTP id x3-20020a5d54c3000000b002102a285666mr13156176wrv.345.1654010568205; Tue, 31 May 2022 08:22:48 -0700 (PDT) Received: from kista.localnet (213-161-3-76.dynamic.telemach.net. [213.161.3.76]) by smtp.gmail.com with ESMTPSA id f6-20020a05600c4e8600b0039466988f6csm3062560wmq.31.2022.05.31.08.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 08:22:47 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Linus Walleij , Chen-Yu Tsai , Samuel Holland Cc: Andre Przywara , Maxime Ripard , Samuel Holland , Krzysztof Kozlowski , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH 0/3] pinctrl: sunxi: Remove non-existent reset line references Date: Tue, 31 May 2022 17:22:46 +0200 Message-ID: <4400164.LvFx2qVVIh@kista> In-Reply-To: <20220531053623.43851-1-samuel@sholland.org> References: <20220531053623.43851-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220531_082252_685983_F647B01E X-CRM114-Status: GOOD ( 20.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Dne torek, 31. maj 2022 ob 07:36:20 CEST je Samuel Holland napisal(a): > I assume these properties came from a lack of documentation, and the > very reasonable assumption that where there's a clock gate bit in the > CCU, there's a reset bit. But the pin controllers are special and don't > have a module reset line. The only way to reset the pin controller is to > reset the whole VDD_SYS power domain. > > This series is preparation for converting the PRCM MFD and legacy clock > drivers to a CCU clock/reset driver like all of the other Allwinner > SoCs. I don't plan to add reset lines that don't actually exist to the > new CCU driver. So we might as well get rid of the references now. > Technically this breaks devicetree compatibility, since the old drivers > expect the reset. But the CCU conversion will be a compatibility break > anyway, so it's a bit of a moot point. If I understand correclty, this would cause only DT forward compatibility issue, which happens now and then anyway. Kernel would still be compatible with older DTs, it would just ignore that reset, right? Best regards, Jernej > > > Samuel Holland (3): > pinctrl: sunxi: Remove reset controller consumers > ARM: dts: sunxi: Drop resets from r_pio nodes > dt-bindings: pinctrl: sunxi: Disallow the resets property > > .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 3 --- > arch/arm/boot/dts/sun6i-a31.dtsi | 1 - > arch/arm/boot/dts/sun8i-a23-a33.dtsi | 1 - > arch/arm/boot/dts/sun9i-a80.dtsi | 1 - > drivers/pinctrl/sunxi/Kconfig | 3 --- > drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 1 - > drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 1 - > drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c | 1 - > drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 22 +--------------- > drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 25 +------------------ > drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c | 1 - > drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c | 1 - > 12 files changed, 2 insertions(+), 59 deletions(-) > > -- > 2.35.1 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel