From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: [PATCH] i386 linux: make 32-bit PAE kernel work when built with newer gcc Date: Fri, 17 Mar 2006 13:28:51 +0100 Message-ID: <441AB993.76F0.0078.0@novell.com> References: <4415AE7C.76F0.0078.0@novell.com> <441AAD1E.76F0.0078.0@novell.com> <107e12b20452b34c59a79771f686802d@cl.cam.ac.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <107e12b20452b34c59a79771f686802d@cl.cam.ac.uk> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Keir Fraser Cc: xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org >Not sure which spec you refer to but it definitely can happen, as >demonstrated by the infamous AMD GART problem some time back: >http://lwn.net/2002/0124/a/athlon-agp-problem.php3 > >The above link gives plenty of detail, but briefly: The processor can >speculatively decide it's found a store instruction and thus >write-allocate an arbitrary cache line. This line will ultimately get >written back even if the speculative store never actually gets >executed. Indeed, then this should be needed on native, too. I have to admit that I hadn't read about x86 processors using speculative writes (Intel's SDM, Vol 3, section 7.2.2 clearly doesn't say anything like that, and AMD doesn't seem to have references to such behavior in their SDM either). Jan