Re: [PATCH] Fix swap entry for MIPS32 36-bit physical address

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From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
To: unlisted-recipients:; (no To-header on input)
Cc: linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
	Pete Popov <ppopov@embeddedalley.com>,
	Jordan Crouse <jordan.crouse@amd.com>
Subject: Re: [PATCH] Fix swap entry for MIPS32 36-bit physical address
Date: Sat, 08 Apr 2006 01:19:11 +0400	[thread overview]
Message-ID: <4436D74F.3040108@ru.mvista.com> (raw)
In-Reply-To: <4436C301.2060001@ru.mvista.com>

Hello.

Sergei Shtylyov wrote:

>>    Additionally, PTEs in MIPS32R2 should have the same layout for the 
>> 36-bit physical address case as in MIPS32R1, according to the 
>> architecture manuals -- so, fix the #ifdef's.

>    I've decided to tead off that part (incomplete anyway) and move it to 
> a separate patch which I'll post shortly.

    I'm really not sure that we need that #if defined(CONFIG_CPU_MIPS32) -- it 
renders CONFIG_64BIT_PHYS_ADDR non-working on all other 32-bit CPUs for which 
Kconfig entry claims that this support exists:

config 64BIT_PHYS_ADDR
         bool "Support for 64-bit physical address space"
         depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || 
CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT

    At least RM7000 has the same PTE layout as MIPS32, I guess the others also 
do. I suspect that the intent was to limit this option to the Alchemy CPUs 
where it's *really* necessary?

WBR, Sergei

WARNING: multiple messages have this Message-ID (diff)

From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
	Pete Popov <ppopov@embeddedalley.com>,
	Jordan Crouse <jordan.crouse@amd.com>
Subject: Re: [PATCH] Fix swap entry for MIPS32 36-bit physical address
Date: Sat, 08 Apr 2006 01:19:11 +0400	[thread overview]
Message-ID: <4436D74F.3040108@ru.mvista.com> (raw)
Message-ID: <20060407211911.7_GpxN5sqWDNFQ7InTRhJDZkzq9lbTNWr5OPao-vRpg@z> (raw)
In-Reply-To: <4436C301.2060001@ru.mvista.com>

Hello.

Sergei Shtylyov wrote:

>>    Additionally, PTEs in MIPS32R2 should have the same layout for the 
>> 36-bit physical address case as in MIPS32R1, according to the 
>> architecture manuals -- so, fix the #ifdef's.

>    I've decided to tead off that part (incomplete anyway) and move it to 
> a separate patch which I'll post shortly.

    I'm really not sure that we need that #if defined(CONFIG_CPU_MIPS32) -- it 
renders CONFIG_64BIT_PHYS_ADDR non-working on all other 32-bit CPUs for which 
Kconfig entry claims that this support exists:

config 64BIT_PHYS_ADDR
         bool "Support for 64-bit physical address space"
         depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || 
CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT

    At least RM7000 has the same PTE layout as MIPS32, I guess the others also 
do. I suspect that the intent was to limit this option to the Alchemy CPUs 
where it's *really* necessary?

WBR, Sergei

next prev parent reply	other threads:[~2006-04-07 21:09 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-02-22 22:20 swapon failure with au1550 Bob Breuer
2005-02-22 22:20 ` Bob Breuer
2006-04-05 13:45 ` [PATCH] Fix swap entry for MIPS32 36-bit physical address Sergei Shtylyov
2006-04-07 19:52   ` Sergei Shtylyov
2006-04-07 21:19     ` Sergei Shtylyov [this message]
2006-04-07 21:19       ` Sergei Shtylyov
2006-04-07 21:20     ` Sergei Shtylyov
2006-04-07 22:04       ` Sergei Shtylyov
2006-04-08  9:51         ` [PATCH] Fix swap entry for MIPS32 with " Sergei Shtylyov
2006-04-08  3:56     ` [PATCH] Enable 36-bit physical address on MIPS32R2 also Sergei Shtylyov

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