RE: swapon failure with au1550

RE: swapon failure with au1550

[Bob Breuer]

The bitmask in a pte for swap type is 0x0000_1f00.  In the CPU_MIPS32 &&
64BIT_PHYS_ADDR case, _PAGE_FILE is 0x0000_0400.  Since _PAGE_FILE is
set in the maxed out swap type, it triggers a BUG().

If I move the swap type field like this:
  #define __swp_type(x)  (((x).val >> 2) & 0x0f)
then it works for me.  This makes use of the _PAGE_DIRTY and _CACHE_MASK
bits which were being used in the !64BIT_PHYS_ADDR case.

Is this a reasonable solution, or should a different grouping of bits be
used?

Bob Breuer

RE: swapon failure with au1550

[Bob Breuer]

The bitmask in a pte for swap type is 0x0000_1f00.  In the CPU_MIPS32 &&
64BIT_PHYS_ADDR case, _PAGE_FILE is 0x0000_0400.  Since _PAGE_FILE is
set in the maxed out swap type, it triggers a BUG().

If I move the swap type field like this:
  #define __swp_type(x)  (((x).val >> 2) & 0x0f)
then it works for me.  This makes use of the _PAGE_DIRTY and _CACHE_MASK
bits which were being used in the !64BIT_PHYS_ADDR case.

Is this a reasonable solution, or should a different grouping of bits be
used?

Bob Breuer

[PATCH] Fix swap entry for MIPS32 36-bit physical address

[Sergei Shtylyov]

[-- Attachment #1: Type: text/plain, Size: 749 bytes --]

Hello.

    With 64-bit physical address enabled, 'swapon' was causing kernel oops
on Alchemy CPUs (MIPS32R1) because of the swap entry type field corrupting the
_PAGE_FILE bit in pte_low. So, change layout of the swap entry to use all bits
except _PAGE_PRESENT and _PAGE_FILE (the harware protection bits are loaded
from pte_high which should be cleared by __swp_entry_to_pte() macro) -- which
gives 25 bits for the swap entry offset.
    Additionally, PTEs in MIPS32R2 should have the same layout for the 36-bit
physical address case as in MIPS32R1, according to the architecture manuals --
so, fix the #ifdef's.

WBR, Sergei

Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>



[-- Attachment #2: MIPS32-36bit-phys-addr-swap-entry-fix.patch --]
[-- Type: text/plain, Size: 3086 bytes --]

diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 0cff64c..89c269f 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -116,7 +116,7 @@ static inline void pmd_clear(pmd_t *pmdp
 	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
 }
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 #define pte_page(x)		pfn_to_page(pte_pfn(x))
 #define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))
 static inline pte_t
@@ -139,7 +139,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot
 #define pte_pfn(x)		((unsigned long)((x).pte >> PAGE_SHIFT))
 #define pfn_pte(pfn, prot)	__pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #endif
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 
 #define __pgd_offset(address)	pgd_index(address)
 #define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
@@ -190,11 +190,27 @@ pfn_pte(unsigned long pfn, pgprot_t prot
 
 #else
 
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+/*
+ * For 36-bit physical address we store swap entry in pte_low and 0 in pte_high,
+ * which gives up 25 bits available for swap offset.
+ */
+#define __swp_type(x)		((x).val & 0x1f)
+#define __swp_offset(x) 	((((x).val >> 5) & 0x1) | \
+				 (((x).val >> 6) & 0xe) | \
+				 (((x).val >> 11) << 4))
+#define __swp_entry(type,offset) \
+		((swp_entry_t) {((type) & 0x1f ) | \
+				(((offset) & 0x1) << 5) | \
+				(((offset) & 0xe) << 6) | \
+				(((offset) >> 4 ) << 11)})
+#else
 /* Swap entries must have VALID and GLOBAL bits cleared. */
 #define __swp_type(x)		(((x).val >> 8) & 0x1f)
 #define __swp_offset(x)		((x).val >> 13)
 #define __swp_entry(type,offset)	\
 		((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 
 /*
  * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
@@ -202,7 +218,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot
  */
 #define PTE_FILE_MAX_BITS	27
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 	/* fixme */
 #define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
 #define pgoff_to_pte(off) \
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 01e76e9..8cbc493 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -33,7 +33,7 @@
  * unpredictable things.  The code (when it is written) to deal with
  * this problem will be in the update_mmu_cache() code for the r4k.
  */
-#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
+#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
 
 #define _PAGE_PRESENT               (1<<6)  /* implemented in software */
 #define _PAGE_READ                  (1<<7)  /* implemented in software */

Re: [PATCH] Fix swap entry for MIPS32 36-bit physical address

[Sergei Shtylyov]

Sergei Shtylyov wrote:
> Hello.
> 
>    With 64-bit physical address enabled, 'swapon' was causing kernel oops
> on Alchemy CPUs (MIPS32R1) because of the swap entry type field 
> corrupting the
> _PAGE_FILE bit in pte_low. So, change layout of the swap entry to use 
> all bits
> except _PAGE_PRESENT and _PAGE_FILE (the harware protection bits are loaded
> from pte_high which should be cleared by __swp_entry_to_pte() macro) -- 
> which gives 25 bits for the swap entry offset.
>    Additionally, PTEs in MIPS32R2 should have the same layout for the 
> 36-bit physical address case as in MIPS32R1, according to the architecture 
> manuals -- so, fix the #ifdef's.

    I've decided to tead off that part (incomplete anyway) and move it to a 
separate patch which I'll post shortly.

> WBR, Sergei
> 
> Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
> 
> 
> 
> ------------------------------------------------------------------------
> 
> diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
> index 0cff64c..89c269f 100644
> --- a/include/asm-mips/pgtable-32.h
> +++ b/include/asm-mips/pgtable-32.h
> @@ -116,7 +116,7 @@ static inline void pmd_clear(pmd_t *pmdp
>  	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
>  }
>  
> -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
> +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
>  #define pte_page(x)		pfn_to_page(pte_pfn(x))
>  #define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))
>  static inline pte_t
> @@ -139,7 +139,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot
>  #define pte_pfn(x)		((unsigned long)((x).pte >> PAGE_SHIFT))
>  #define pfn_pte(pfn, prot)	__pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
>  #endif
> -#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
> +#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
>  
>  #define __pgd_offset(address)	pgd_index(address)
>  #define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
> @@ -190,11 +190,27 @@ pfn_pte(unsigned long pfn, pgprot_t prot
>  
>  #else
>  
> +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
> +/*
> + * For 36-bit physical address we store swap entry in pte_low and 0 in pte_high,
> + * which gives up 25 bits available for swap offset.
> + */
> +#define __swp_type(x)		((x).val & 0x1f)
> +#define __swp_offset(x) 	((((x).val >> 5) & 0x1) | \
> +				 (((x).val >> 6) & 0xe) | \
> +				 (((x).val >> 11) << 4))
> +#define __swp_entry(type,offset) \
> +		((swp_entry_t) {((type) & 0x1f ) | \
> +				(((offset) & 0x1) << 5) | \
> +				(((offset) & 0xe) << 6) | \
> +				(((offset) >> 4 ) << 11)})
> +#else
>  /* Swap entries must have VALID and GLOBAL bits cleared. */
>  #define __swp_type(x)		(((x).val >> 8) & 0x1f)
>  #define __swp_offset(x)		((x).val >> 13)
>  #define __swp_entry(type,offset)	\
>  		((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
> +#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
>  
>  /*
>   * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
> @@ -202,7 +218,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot
>   */
>  #define PTE_FILE_MAX_BITS	27
>  
> -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
> +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
>  	/* fixme */
>  #define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
>  #define pgoff_to_pte(off) \
> diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
> index 01e76e9..8cbc493 100644
> --- a/include/asm-mips/pgtable-bits.h
> +++ b/include/asm-mips/pgtable-bits.h
> @@ -33,7 +33,7 @@
>   * unpredictable things.  The code (when it is written) to deal with
>   * this problem will be in the update_mmu_cache() code for the r4k.
>   */
> -#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
> +#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
>  
>  #define _PAGE_PRESENT               (1<<6)  /* implemented in software */
>  #define _PAGE_READ                  (1<<7)  /* implemented in software */
> 
> 

Re: [PATCH] Fix swap entry for MIPS32 36-bit physical address

[Sergei Shtylyov]

Hello.

Sergei Shtylyov wrote:

>>    Additionally, PTEs in MIPS32R2 should have the same layout for the 
>> 36-bit physical address case as in MIPS32R1, according to the 
>> architecture manuals -- so, fix the #ifdef's.

>    I've decided to tead off that part (incomplete anyway) and move it to 
> a separate patch which I'll post shortly.

    I'm really not sure that we need that #if defined(CONFIG_CPU_MIPS32) -- it 
renders CONFIG_64BIT_PHYS_ADDR non-working on all other 32-bit CPUs for which 
Kconfig entry claims that this support exists:

config 64BIT_PHYS_ADDR
         bool "Support for 64-bit physical address space"
         depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || 
CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT

    At least RM7000 has the same PTE layout as MIPS32, I guess the others also 
do. I suspect that the intent was to limit this option to the Alchemy CPUs 
where it's *really* necessary?

WBR, Sergei

Re: [PATCH] Fix swap entry for MIPS32 36-bit physical address

[Sergei Shtylyov]

Hello.

Sergei Shtylyov wrote:

>>    Additionally, PTEs in MIPS32R2 should have the same layout for the 
>> 36-bit physical address case as in MIPS32R1, according to the 
>> architecture manuals -- so, fix the #ifdef's.

>    I've decided to tead off that part (incomplete anyway) and move it to 
> a separate patch which I'll post shortly.

    I'm really not sure that we need that #if defined(CONFIG_CPU_MIPS32) -- it 
renders CONFIG_64BIT_PHYS_ADDR non-working on all other 32-bit CPUs for which 
Kconfig entry claims that this support exists:

config 64BIT_PHYS_ADDR
         bool "Support for 64-bit physical address space"
         depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || 
CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT

    At least RM7000 has the same PTE layout as MIPS32, I guess the others also 
do. I suspect that the intent was to limit this option to the Alchemy CPUs 
where it's *really* necessary?

WBR, Sergei

Re: [PATCH] Fix swap entry for MIPS32 36-bit physical address

[Sergei Shtylyov]

[-- Attachment #1: Type: text/plain, Size: 568 bytes --]

Hello.

    With 64-bit physical address enabled, 'swapon' was causing kernel oops
on Alchemy CPUs (MIPS32) because of the swap entry type field corrupting the
_PAGE_FILE bit in pte_low. So, change layout of the swap entry to use all bits
except _PAGE_PRESENT and _PAGE_FILE (the harware protection bits are loaded
from pte_high which should be cleared by __swp_entry_to_pte() macro) -- which
gives 25 bits for the swap entry offset.

WBR, Sergei

Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>



[-- Attachment #2: MIPS32-36bit-phys-addr-swap-entry-fix.patch --]
[-- Type: text/plain, Size: 1202 bytes --]

diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 4d6bc45..b0ad112 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -190,11 +190,27 @@ pfn_pte(unsigned long pfn, pgprot_t prot
 
 #else
 
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+/*
+ * For 36-bit physical address we store swap entry in pte_low and 0 in pte_high,
+ * which gives us 25 bits available for the offset...
+ */
+#define __swp_type(x)		((x).val & 0x1f)
+#define __swp_offset(x) 	((((x).val >> 5) & 0x1) | \
+				 (((x).val >> 6) & 0xe) | \
+				 (((x).val >> 11) << 4))
+#define __swp_entry(type,offset)	\
+		((swp_entry_t) { ((type) & 0x1f) | \
+				 (((offset) & 0x1) << 5) | \
+				 (((offset) & 0xe) << 6) | \
+				 (((offset) >> 4 ) << 11) })
+#else
 /* Swap entries must have VALID and GLOBAL bits cleared. */
 #define __swp_type(x)		(((x).val >> 8) & 0x1f)
 #define __swp_offset(x)		((x).val >> 13)
 #define __swp_entry(type,offset)	\
 		((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 
 /*
  * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset

Re: [PATCH] Fix swap entry for MIPS32 36-bit physical address

[Sergei Shtylyov]

Hello.

Sergei Shtylyov wrote:

>    With 64-bit physical address enabled, 'swapon' was causing kernel oops
> on Alchemy CPUs (MIPS32) because of the swap entry type field corrupting 
> the _PAGE_FILE bit in pte_low. So, change layout of the swap entry to use 
> all bits
> except _PAGE_PRESENT and _PAGE_FILE (the harware protection bits are loaded
> from pte_high which should be cleared by __swp_entry_to_pte() macro) -- 
> which gives 25 bits for the swap entry offset.

    Hm, just noticed that this fix renders set_pte()/pte_clear() erroneous by 
reusing _PAGE_GLOBAL (bit 0) in pte_low field of pte_t -- pte_high should have 
been used instead or those macros fixed. So, refrain from committing as yet...

WBR, Sergei

> Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>

> ------------------------------------------------------------------------
> 
> diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
> index 4d6bc45..b0ad112 100644
> --- a/include/asm-mips/pgtable-32.h
> +++ b/include/asm-mips/pgtable-32.h
> @@ -190,11 +190,27 @@ pfn_pte(unsigned long pfn, pgprot_t prot
>  
>  #else
>  
> +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
> +/*
> + * For 36-bit physical address we store swap entry in pte_low and 0 in pte_high,
> + * which gives us 25 bits available for the offset...
> + */
> +#define __swp_type(x)		((x).val & 0x1f)
> +#define __swp_offset(x) 	((((x).val >> 5) & 0x1) | \
> +				 (((x).val >> 6) & 0xe) | \
> +				 (((x).val >> 11) << 4))
> +#define __swp_entry(type,offset)	\
> +		((swp_entry_t) { ((type) & 0x1f) | \
> +				 (((offset) & 0x1) << 5) | \
> +				 (((offset) & 0xe) << 6) | \
> +				 (((offset) >> 4 ) << 11) })
> +#else
>  /* Swap entries must have VALID and GLOBAL bits cleared. */
>  #define __swp_type(x)		(((x).val >> 8) & 0x1f)
>  #define __swp_offset(x)		((x).val >> 13)
>  #define __swp_entry(type,offset)	\
>  		((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
> +#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
>  
>  /*
>   * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
> 
> 

Re: [PATCH] Enable 36-bit physical address on MIPS32R2 also

[Sergei Shtylyov]

[-- Attachment #1: Type: text/plain, Size: 314 bytes --]

Hello.

    PTEs in MIPS32R2 have the same layout for the 36-bit physical address case
as in MIPS32R1, according to the architecture manuals -- so, fix the #if's.
    Not sure that we need that #if defined(CONFIG_CPU_MIPS32) at all though...

WBR, Sergei

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>


[-- Attachment #2: MIPS32R2-36bit-phys-addr.patch --]
[-- Type: text/plain, Size: 4367 bytes --]

diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 4d6bc45..5f31351 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -116,7 +116,7 @@ static inline void pmd_clear(pmd_t *pmdp
 	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
 }
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 #define pte_page(x)		pfn_to_page(pte_pfn(x))
 #define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))
 static inline pte_t
@@ -137,9 +137,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot
 #define pfn_pte(pfn, prot)	__pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
 #else
 #define pte_pfn(x)		((unsigned long)((x).pte >> PAGE_SHIFT))
-#define pfn_pte(pfn, prot)	__pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #endif
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 
 #define __pgd_offset(address)	pgd_index(address)
 #define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
@@ -202,7 +202,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot
  */
 #define PTE_FILE_MAX_BITS	27
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 	/* fixme */
 #define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
 #define pgoff_to_pte(off) \
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 01e76e9..3aad751 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -33,7 +33,7 @@
  * unpredictable things.  The code (when it is written) to deal with
  * this problem will be in the update_mmu_cache() code for the r4k.
  */
-#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
+#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
 
 #define _PAGE_PRESENT               (1<<6)  /* implemented in software */
 #define _PAGE_READ                  (1<<7)  /* implemented in software */
@@ -123,7 +123,7 @@
 
 #endif
 #endif
-#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
+#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */
 
 #define __READABLE	(_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
 #define __WRITEABLE	(_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -140,7 +140,7 @@
 #define PAGE_CACHABLE_DEFAULT	_CACHE_CACHABLE_COW
 #endif
 
-#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
+#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
 #define CONF_CM_DEFAULT		(PAGE_CACHABLE_DEFAULT >> 3)
 #else
 #define CONF_CM_DEFAULT		(PAGE_CACHABLE_DEFAULT >> 9)
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 702a28f..925211d 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -85,7 +85,7 @@ extern void paging_init(void);
 #define pte_none(pte)		(!(pte_val(pte) & ~_PAGE_GLOBAL))
 #define pte_present(pte)	(pte_val(pte) & _PAGE_PRESENT)
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 static inline void set_pte(pte_t *ptep, pte_t pte)
 {
 	ptep->pte_high = pte.pte_high;
@@ -173,7 +173,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD
  * Undefined behaviour if not..
  */
 static inline int pte_user(pte_t pte)	{ BUG(); return 0; }
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 static inline int pte_read(pte_t pte)	{ return (pte).pte_low & _PAGE_READ; }
 static inline int pte_write(pte_t pte)	{ return (pte).pte_low & _PAGE_WRITE; }
 static inline int pte_dirty(pte_t pte)	{ return (pte).pte_low & _PAGE_MODIFIED; }
@@ -332,7 +332,7 @@ static inline pgprot_t pgprot_noncached(
  */
 #define mk_pte(page, pgprot)	pfn_pte(page_to_pfn(page), (pgprot))
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
 	pte.pte_low &= _PAGE_CHG_MASK;

[PATCH] Fix swap entry for MIPS32 with 36-bit physical address

[Sergei Shtylyov]

[-- Attachment #1: Type: text/plain, Size: 420 bytes --]


     With 64-bit physical address enabled, 'swapon' was causing kernel oops on
Alchemy CPUs (MIPS32) because of the swap entry type field corrupting the
_PAGE_FILE bit in 'pte_low' field. So, switch to storing the swap entry in
'pte_high' field using all its bits except _PAGE_GLOBAL and _PAGE_VALID which
gives 25 bits for the swap entry offset.

WBR, Sergei

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>


[-- Attachment #2: MIPS32-36bit-phys-addr-swap-entry-fix.patch --]
[-- Type: text/plain, Size: 1433 bytes --]

diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 4d6bc45..a5ce3f1 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -191,10 +191,17 @@ pfn_pte(unsigned long pfn, pgprot_t prot
 #else
 
 /* Swap entries must have VALID and GLOBAL bits cleared. */
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#define __swp_type(x)		(((x).val >> 2) & 0x1f)
+#define __swp_offset(x) 	 ((x).val >> 7)
+#define __swp_entry(type,offset)	\
+		((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
+#else
 #define __swp_type(x)		(((x).val >> 8) & 0x1f)
-#define __swp_offset(x)		((x).val >> 13)
+#define __swp_offset(x) 	 ((x).val >> 13)
 #define __swp_entry(type,offset)	\
-		((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
+		((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 
 /*
  * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
@@ -218,7 +225,12 @@ pfn_pte(unsigned long pfn, pgprot_t prot
 
 #endif
 
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
+#define __swp_entry_to_pte(x)	((pte_t) { 0, (x).val })
+#else
 #define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
 #define __swp_entry_to_pte(x)	((pte_t) { (x).val })
+#endif
 
 #endif /* _ASM_PGTABLE_32_H */