Hi,

while playing with different -march options of MIPS GCC, I
found that  GCC generates some special R5400 three register
multiply assembly commands if used with -march=vr5400 (MULS,
MULHI, MACC etc.). These commands use 11 bit extended
opcodes where the lowest 6 bits are the same as for the
standard MULT/MULTU instructions (0x18 & 0x19). See for
example chapter 17.4 of

www.necelam.com/docs/files/1375_V2.pdf

Unfortunately, because QEMU uses mask 0x3F to extract
opcode, it doesn't detect these special opcodes and instead
executes the (wrong) standard ones. No exception or
warning is given. Calculation is simply wrong and program
misbehaves while working with wrong values.

Patch below adds support for these special MIPS opcodes.

Regards

Dirk