From: Nick Piggin <nickpiggin@yahoo.com.au>
To: Andi Kleen <ak@suse.de>
Cc: Chris Wright <chrisw@sous-sol.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
zach@vmware.com, torvalds@osdl.org
Subject: Re: [PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
Date: Fri, 28 Apr 2006 17:20:29 +1000 [thread overview]
Message-ID: <4451C23D.5000002@yahoo.com.au> (raw)
In-Reply-To: <200604280829.29164.ak@suse.de>
Andi Kleen wrote:
> No it was me who was confused sorry. Somehow i thought it was defined
> away for !SMP
>
> (which would make sense because why would you want a compile barrier
> for a barrier that is only needed on SMP?)
It is maybe not clearly named. smp_wmb() is a memory barrier to the
regular (eg. RAM) cache coherency domain AFAICT. wmb() is also a
barrier to io memory.
There is nothing to distinguish SMP and UP. I guess sometimes smp_
barriers would not even have to be a barrier() on UP, but other
times they would have to be (eg. in the case of concurrent
interrupts, context switches).
--
SUSE Labs, Novell Inc.
Send instant messages to your online friends http://au.messenger.yahoo.com
next prev parent reply other threads:[~2006-04-28 7:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200604272001.k3RK1dmX007637@hera.kernel.org>
2006-04-28 5:18 ` [PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case Andi Kleen
2006-04-28 5:23 ` Chris Wright
2006-04-28 6:08 ` Andi Kleen
2006-04-28 6:27 ` Chris Wright
2006-04-28 6:29 ` Andi Kleen
2006-04-28 7:20 ` Nick Piggin [this message]
2006-04-28 14:54 ` Linus Torvalds
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