diff for duplicates of <4452066.ogQpVHnZLL@flatron> diff --git a/a/1.txt b/N1/1.txt index b631090..4f57a42 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -31,7 +31,7 @@ On Friday 02 of August 2013 19:25:25 Tero Kristo wrote: > * published by the Free Software Foundation. > + */ > + -> +bandgap_fclk: bandgap_fclk@4a307888 { +> +bandgap_fclk: bandgap_fclk at 4a307888 { > + #clock-cells = <0>; > + compatible = "gate-clock"; > + clocks = <&sys_32k_ck>; @@ -88,7 +88,7 @@ On Friday 02 of August 2013 19:25:25 Tero Kristo wrote: > * published by the Free Software Foundation. > + */ > + -> +div_ts_ck: div_ts_ck@4a307888 { +> +div_ts_ck: div_ts_ck at 4a307888 { > + #clock-cells = <0>; > + compatible = "divider-clock"; > + clocks = <&l4_wkup_clk_mux_ck>; @@ -98,7 +98,7 @@ On Friday 02 of August 2013 19:25:25 Tero Kristo wrote: > + bit-mask = <0x3>; > +}; > + -> +bandgap_ts_fclk: bandgap_ts_fclk@4a307888 { +> +bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 { > + #clock-cells = <0>; > + compatible = "gate-clock"; > + clocks = <&div_ts_ck>; @@ -133,7 +133,7 @@ On Friday 02 of August 2013 19:25:25 Tero Kristo wrote: > + clock-frequency = <12000000>; > +}; > + -> +pad_clks_ck: pad_clks_ck@4a004108 { +> +pad_clks_ck: pad_clks_ck at 4a004108 { > + #clock-cells = <0>; > + compatible = "gate-clock"; > + clocks = <&pad_clks_src_ck>; @@ -159,7 +159,7 @@ On Friday 02 of August 2013 19:25:25 Tero Kristo wrote: > + clock-frequency = <12000000>; > +}; > + -> +slimbus_clk: slimbus_clk@4a004108 { +> +slimbus_clk: slimbus_clk at 4a004108 { > + #clock-cells = <0>; > + compatible = "gate-clock"; > + clocks = <&slimbus_src_clk>; @@ -215,7 +215,7 @@ On Friday 02 of August 2013 19:25:25 Tero Kristo wrote: > + clock-frequency = <38400000>; > +}; > + -> +sys_clkin_ck: sys_clkin_ck@4a306110 { +> +sys_clkin_ck: sys_clkin_ck at 4a306110 { > + #clock-cells = <0>; > + compatible = "mux-clock"; > + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, @@ -255,7 +255,7 @@ On Friday 02 of August 2013 19:25:25 Tero Kristo wrote: > + clock-frequency = <60000000>; > +}; > + -> +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 { +> +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 { > + #clock-cells = <0>; > + compatible = "mux-clock"; > + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -264,7 +264,7 @@ On Friday 02 of August 2013 19:25:25 Tero Kristo wrote: > + bit-mask = <0x1>; > +}; > + -> +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@4a30610c { +> +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c { > + #clock-cells = <0>; > + compatible = "mux-clock"; > + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -272,7 +272,7 @@ On Friday 02 of August 2013 19:25:25 Tero Kristo wrote: > + bit-mask = <0x1>; > +}; > + -> +dpll_abe_ck: dpll_abe_ck@4a0041e0 { +> +dpll_abe_ck: dpll_abe_ck at 4a0041e0 { > + #clock-cells = <0>; > + compatible = "ti,omap4-dpll-m4xen-clock"; > + clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; diff --git a/a/content_digest b/N1/content_digest index e50d146..90c83a6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,9 @@ "ref\01375460751-23676-1-git-send-email-t-kristo@ti.com\0" "ref\01375460751-23676-7-git-send-email-t-kristo@ti.com\0" - "From\0Tomasz Figa <tomasz.figa@gmail.com>\0" - "Subject\0Re: [PATCHv5 06/31] ARM: dts: omap4 clock data\0" + "From\0tomasz.figa@gmail.com (Tomasz Figa)\0" + "Subject\0[PATCHv5 06/31] ARM: dts: omap4 clock data\0" "Date\0Sat, 03 Aug 2013 16:16:21 +0200\0" - "To\0Tero Kristo <t-kristo@ti.com>\0" - "Cc\0linux-omap@vger.kernel.org" - paul@pwsan.com - tony@atomide.com - nm@ti.com - rnayak@ti.com - mturquette@linaro.org - linux-arm-kernel@lists.infradead.org - " devicetree@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Friday 02 of August 2013 19:25:25 Tero Kristo wrote:\n" @@ -47,7 +39,7 @@ "> * published by the Free Software Foundation.\n" "> + */\n" "> +\n" - "> +bandgap_fclk: bandgap_fclk@4a307888 {\n" + "> +bandgap_fclk: bandgap_fclk at 4a307888 {\n" "> +\t#clock-cells = <0>;\n" "> +\tcompatible = \"gate-clock\";\n" "> +\tclocks = <&sys_32k_ck>;\n" @@ -104,7 +96,7 @@ "> * published by the Free Software Foundation.\n" "> + */\n" "> +\n" - "> +div_ts_ck: div_ts_ck@4a307888 {\n" + "> +div_ts_ck: div_ts_ck at 4a307888 {\n" "> +\t#clock-cells = <0>;\n" "> +\tcompatible = \"divider-clock\";\n" "> +\tclocks = <&l4_wkup_clk_mux_ck>;\n" @@ -114,7 +106,7 @@ "> +\tbit-mask = <0x3>;\n" "> +};\n" "> +\n" - "> +bandgap_ts_fclk: bandgap_ts_fclk@4a307888 {\n" + "> +bandgap_ts_fclk: bandgap_ts_fclk at 4a307888 {\n" "> +\t#clock-cells = <0>;\n" "> +\tcompatible = \"gate-clock\";\n" "> +\tclocks = <&div_ts_ck>;\n" @@ -149,7 +141,7 @@ "> +\tclock-frequency = <12000000>;\n" "> +};\n" "> +\n" - "> +pad_clks_ck: pad_clks_ck@4a004108 {\n" + "> +pad_clks_ck: pad_clks_ck at 4a004108 {\n" "> +\t#clock-cells = <0>;\n" "> +\tcompatible = \"gate-clock\";\n" "> +\tclocks = <&pad_clks_src_ck>;\n" @@ -175,7 +167,7 @@ "> +\tclock-frequency = <12000000>;\n" "> +};\n" "> +\n" - "> +slimbus_clk: slimbus_clk@4a004108 {\n" + "> +slimbus_clk: slimbus_clk at 4a004108 {\n" "> +\t#clock-cells = <0>;\n" "> +\tcompatible = \"gate-clock\";\n" "> +\tclocks = <&slimbus_src_clk>;\n" @@ -231,7 +223,7 @@ "> +\tclock-frequency = <38400000>;\n" "> +};\n" "> +\n" - "> +sys_clkin_ck: sys_clkin_ck@4a306110 {\n" + "> +sys_clkin_ck: sys_clkin_ck at 4a306110 {\n" "> +\t#clock-cells = <0>;\n" "> +\tcompatible = \"mux-clock\";\n" "> +\tclocks = <&virt_12000000_ck>, <&virt_13000000_ck>,\n" @@ -271,7 +263,7 @@ "> +\tclock-frequency = <60000000>;\n" "> +};\n" "> +\n" - "> +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {\n" + "> +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {\n" "> +\t#clock-cells = <0>;\n" "> +\tcompatible = \"mux-clock\";\n" "> +\tclocks = <&sys_clkin_ck>, <&sys_32k_ck>;\n" @@ -280,7 +272,7 @@ "> +\tbit-mask = <0x1>;\n" "> +};\n" "> +\n" - "> +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@4a30610c {\n" + "> +abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck at 4a30610c {\n" "> +\t#clock-cells = <0>;\n" "> +\tcompatible = \"mux-clock\";\n" "> +\tclocks = <&sys_clkin_ck>, <&sys_32k_ck>;\n" @@ -288,7 +280,7 @@ "> +\tbit-mask = <0x1>;\n" "> +};\n" "> +\n" - "> +dpll_abe_ck: dpll_abe_ck@4a0041e0 {\n" + "> +dpll_abe_ck: dpll_abe_ck at 4a0041e0 {\n" "> +\t#clock-cells = <0>;\n" "> +\tcompatible = \"ti,omap4-dpll-m4xen-clock\";\n" "> +\tclocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;\n" @@ -305,4 +297,4 @@ "Best regards,\n" Tomasz -ca7d1c5d5ca741dec07240e5071e66cb54428655db69cfe3f14da497f9e058bb +eb4953b329eeaefae3cd3520786338d682038564f0f9f1c3dc088b13d8d601cb
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