Re: [Qemu-devel] [PATCH] Fix overflow conditions for MIPS add/subtract

[Stefan Weil <weil@mail.berlios.de>]

Dirk Behme schrieb:

 >
 > Fix overflow conditions for MIPS add/subtract as proposed by
 > Daniel Jacobowitz.
 >
 > http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00538.html
 >
 > Regards
 >
 > Dirk
 >
 >------------------------------------------------------------------------
 >
 >--- target-mips/op.c_orig 2006-04-30 09:40:46.000000000 +0200
 >+++ target-mips/op.c 2006-04-30 09:41:52.000000000 +0200
 >@@ -206,7 +206,7 @@ void op_addo (void)
 >
 > tmp = T0;
 > T0 += T1;
 >- if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
 >+ if (~(T0 ^ T1) & (T0 ^ tmp) & 0x80000000) {
 > /* operands of same sign, result different sign */
 > CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
 > }
 >@@ -225,7 +225,7 @@ void op_subo (void)
 >
 > tmp = T0;
 > T0 = (int32_t)T0 - (int32_t)T1;
 >- if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
 >+ if ((T0 ^ T1) & (T0 ^ tmp) & 0x80000000) {
 > /* operands of different sign, first operand and result different sign */
 > CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
 > }
 >
 >
 >
 >
 >------------------------------------------------------------------------
 >
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 >Qemu-devel mailing list
 >Qemu-devel@nongnu.org
 >http://lists.nongnu.org/mailman/listinfo/qemu-devel
 >
 >

Hello Dirk,

which additions / subtractions are handled incorrectly by the current code?
Here is the result of a test which shows that the current code (which is
based on my patch)
raises an exception for 0x80000000 + 0x80000000.

Daniel, perhaps you could sent the code you used to check overflow
conditions?
Maybe there is no need to change functions op_addo and op_subo for MIPS.

Regards
Stefan

IN:
0x94000000: lui v0,0x8000
0x94000004: lui v1,0x8000
0x94000008: add a0,v0,v1
0x9400000c: b 0x9400000c
0x94000010: nop

---------------- 2 00000002
do_raise_exception_err: 19 0
do_interrupt enter: PC 94000008 EPC 00000000 cause -1 excp 19
do_interrupt: PC bfc00380 EPC 94000008 cause 12 excp 19
S 10400000 C 00000030 A 00000000 D 00000000
cpu_mips_handle_mmu_fault pc bfc00380 ad bfc00380 rw 2 is_user 0 smmu 1
cpu_mips_handle_mmu_fault address=bfc00380 ret 0 physical 1fc00380 prot 1
------------------------------------------------
pc=0xbfc00380 HI=0x00000000 LO=0x00000000 ds 0006 00000000 0
GPR00: r0 00000000 at 00000000 v0 80000000 v1 80000000
GPR04: a0 00000000 a1 00000000 a2 00000000 a3 00000000
GPR08: t0 00000000 t1 00000000 t2 00000000 t3 00000000
GPR12: t4 00000000 t5 00000000 t6 00000000 t7 00000000
GPR16: s0 00000000 s1 00000000 s2 00000000 s3 00000000
GPR20: s4 00000000 s5 00000000 s6 00000000 s7 00000000
GPR24: t8 00000000 t9 00000000 k0 00000000 k1 00000000
GPR28: gp 00000000 sp 94001040 s8 00000000 ra 00000000
CP0 Status 0x10400006 Cause 0x00000030 EPC 0x94000008
Config0 0x80008090 Config1 0x1e9b4d8a LLAddr 0x00000000