From: John Miller <jamiller1110@cox.net>
To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc: linux-mips@linux-mips.org
Subject: Re: Instruction error with cache opcode
Date: Sun, 14 May 2006 21:35:10 -0400 [thread overview]
Message-ID: <4467DACE.9000800@mountolympos.net> (raw)
In-Reply-To: <20060515.100659.126574393.nemoto@toshiba-tops.co.jp>
Atsushi Nemoto wrote:
> On Sun, 14 May 2006 14:39:42 -0400, John Miller <jamiller1110@cox.net> wrote:
>
>> I included asm/cacheops.h from the kernel tree, it is defined there as :
>>
>> #define Index_Store_Tag_I 0x08
>>
>
> Then how about Fill_I ?
>
> ---
> Atsushi Nemoto
>
That got it! Sorry, I had my head up somewhere it was not supposed to
be. I do not know how many times I went over cacheops.h and missed the
fact that Fill was defined, not Fill_I. One I changed my code to Fill,
it built the kernel nicely. It still died before the first printk :)
but at least I am a little closer. I got Fill_I out of the See MIPS Run
book, it has the same option hex (0x14) as Fill, does anyone know why
this changed?
next prev parent reply other threads:[~2006-05-15 1:35 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-05-14 13:51 Instruction error with cache opcode John Miller
2006-05-14 13:51 ` John Miller
2006-05-14 14:17 ` Kevin D. Kissell
2006-05-14 14:17 ` Kevin D. Kissell
2006-05-14 18:39 ` John Miller
2006-05-14 19:42 ` Kevin D. Kissell
2006-05-14 19:42 ` Kevin D. Kissell
2006-05-14 20:14 ` John Miller
2006-05-14 23:29 ` Thiemo Seufer
2006-05-15 1:06 ` Atsushi Nemoto
2006-05-15 1:35 ` John Miller [this message]
2006-05-15 1:38 ` John Miller
2006-05-15 1:38 ` John Miller
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