[Qemu-devel][PATCH] Fix initial value for MIPS CP0 Config Register

[Stefan Weil <weil@mail.berlios.de>]

Hi,

this patch fixes several bugs in mips-defs.h:

* Using enum for MIPS_R4Kc, MIPS_R4Kp does not work as  expected,
  because the C preprocessor does not know these values. It will
  always use the branch for MIPS_R4Kc - independent of MIPS_CPU.

* More important is the value of the CP0 config register.
  The lower three bits CPC0_K0 have an initial value of 010 (binary),
  not 0x010 (hex), so they must be 2.
  I also changed the 3 digit hex numbers to 1 digit decimal numbers
  because these fields only need 1, 2 or 3 bits.

* Spelling was fixed.

Regards
Stefan

Index: target-mips/mips-defs.h
===================================================================
RCS file: /sources/qemu/qemu/target-mips/mips-defs.h,v
retrieving revision 1.1
diff -u -b -B -u -r1.1 mips-defs.h
--- target-mips/mips-defs.h     2 Jul 2005 14:57:14 -0000       1.1
+++ target-mips/mips-defs.h     19 May 2006 21:03:29 -0000
@@ -6,10 +6,8 @@
 /* If we want to use host float regs... */
 //#define USE_HOST_FLOAT_REGS

-enum {
-    MIPS_R4Kc = 0x00018000,
-    MIPS_R4Kp = 0x00018300,
-};
+#define MIPS_R4Kc 0x00018000
+#define MIPS_R4Kp 0x00018300

 /* Emulate MIPS R4Kc for now */
 #define MIPS_CPU MIPS_R4Kc
@@ -19,15 +17,15 @@
 #define TARGET_LONG_BITS 32
 /* real pages are variable size... */
 #define TARGET_PAGE_BITS 12
-/* Uses MIPS R4Kx ehancements to MIPS32 architecture */
+/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
 #define MIPS_USES_R4K_EXT
 /* Uses MIPS R4Kc TLB model */
 #define MIPS_USES_R4K_TLB
 #define MIPS_TLB_NB 16
 /* Have config1, runs in big-endian mode, uses TLB */
 #define MIPS_CONFIG0                                            \
-((1 << CP0C0_M) | (0x000 << CP0C0_K23) | (0x000 << CP0C0_KU) |  \
- (1 << CP0C0_BE) | (0x001 << CP0C0_MT) | (0x010 << CP0C0_K0))
+((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) |  \
+ (1 << CP0C0_BE) | (1 << CP0C0_MT) | (2 << CP0C0_K0))
 /* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
  * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
  * no performance counters, watch registers present, no code compression,
@@ -44,7 +42,7 @@
 #define TARGET_LONG_BITS 32
 /* real pages are variable size... */
 #define TARGET_PAGE_BITS 12
-/* Uses MIPS R4Kx ehancements to MIPS32 architecture */
+/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
 #define MIPS_USES_R4K_EXT
 /* Uses MIPS R4Km FPM MMU model */
 #define MIPS_USES_R4K_FPM