Re: [MIPS] Fix swap entry for MIPS32 36-bit physical address

[Sergei Shtylyov <sshtylyov@ru.mvista.com>]

Hello.

linux-mips@linux-mips.org wrote:
> Author: Sergei Shtylyov <sshtylyov@ru.mvista.com> Wed Apr 5 00:24:40 2006 +0400
> Comitter: Ralf Baechle <ralf@linux-mips.org> Sat May 27 00:01:23 2006 +0100
> Commit: f826429f5ad38f40b96ff587cd44def138f99f3a
> Gitweb: http://www.linux-mips.org/g/linux/f826429f
> Branch: master
> 
> With 64-bit physical address enabled, 'swapon' was causing kernel oops
> on Alchemy CPUs (MIPS32R1) because of the swap entry type field
> corrupting the _PAGE_FILE bit in pte_low. So, change layout of the
> swap entry to use all bits except _PAGE_PRESENT and _PAGE_FILE (the
> hardware protection bits are loaded from pte_high which should be
> cleared by __swp_entry_to_pte() macro) -- which gives 25 bits for the
> swap entry offset.  Additionally, PTEs in MIPS32R2 should have the same
> layout for 64-bit physical address case as in MIPS32R1, according to
> the architecture manuals -- so, fix the #ifdef's.
> 
> Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
> 
> ---
> 
>  include/asm-mips/pgtable-32.h   |   22 +++++++++++++++++++---
>  include/asm-mips/pgtable-bits.h |    2 +-
>  2 files changed, 20 insertions(+), 4 deletions(-)

    Alas, Ralf have finally managed to commit the wrong patch -- both outdated 
and error-prone because it reuses _PAGE_GLOBAL which is bad for set_pte() and 
pte_clear() and probably for the CPU itself since it ANDs G-bit of both the 
even and odd PTEs to decide whether to compare ASID or not when doing TLB 
lookups. I wonder whether this commit can be undone (it's still the most 
recent one) or should I compose an incremental patch?

WBR, Sergei