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Date: Wed, 21 Jun 2006 18:46:38 +1000
From: Aidan Williams <aidan@nicta.com.au>
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To: Rick Moleres <rick.moleres@xilinx.com>
Subject: Re: Linux on Virtex4
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Cc: linuxppc-embedded@ozlabs.org, "Martin, Tim" <tim.martin@viasat.com>
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Rick Moleres wrote:
> There's also a Linux 2.4 patch provided with the ML403 PPC reference
> design on the Xilinx website
> (http://www.xilinx.com/products/boards/ml403/reference_designs.htm) that
> takes care of a Virtex-4 PPC cache issue (CCR0 register).  Have you
> applied this?
> 

Rick, which cache issue are you referring to?

I tried setting the CCR0 bits in accordance with:

   "Solution 10: CPU_213: Incorrect data might be
    flushed from the data cache"

but that didn't fix things in my case for the Avnet FX12 MiniModule.


I'm pretty sure that the FX12-MM strikes:

   "Solution 13: The return of a cacheline transaction that
    is not target word first (non-target word first) can
    cause data corruption in the PPC405 Core data cache in
    Virtex-4 FX devices."

For which the only solutions mentioned are to run without caches or get 
a fixed chip.


As I understand it, the memory controller for this board must be on the 
OPB because the memory is 16-bit.  Is there any way to move the memory 
controller to the PLB thus avoiding the cache problem (for RAM at least)?

- aidan