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From: Dirk Behme <dirk.behme@googlemail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] Wrong reset of MIPS hflags EXL after interrupt?
Date: Wed, 16 Aug 2006 19:04:10 +0200	[thread overview]
Message-ID: <44E3500A.4050608@gmail.com> (raw)

Hi,

I'm not sure, but while playing with MIPS interrupts, it 
seems to me that something with reset of interrupt flag 
MIPS_HFLAG_EXL (0x04) at exception exit (eret) is wrong. It 
seems to me that only one interrupt is executed because 
after eret, MIPS_HFLAG_EXL stays set in env->hflags. Then, 
at next interrupt, system correctly checks for 
MIPS_HFLAG_EXL, but this is still set and no further 
interrupt happens.

Debugging shows that op_eret() in MIPS op.c correctly reset 
this bit: env->hflags &= ~MIPS_HFLAG_EXL; But debug output 
at end of e.g. save_cpu_state() (debug output of ctx->hflags 
and ctx->saved_hflags ) or in function which tries to issue 
(next) timer interrupt (debug output of env->hflags) 
MIPS_HFLAG_EXL is still (again?) set everywhere. Looks like 
the correct env->hflags from op_eret() is overwritten 
somewhere later with wrong value.

These three ctx->hflags, ctx->saved_hflags and env->hflags 
are confusing me ;) Where are they synchronized after eret? 
Or who overwrites the env->hflags correctly set by eret 
again? Any ideas, why eret sets env->hflags correctly and 
later global env->hflags has still/again wrong value? Any 
other hints?

Many thanks

Dirk

Debug output shows something like:

save_cpu_state(): ctx->hflags 00000000 ctx->saved_hflags 
00000000
MIPS Timer #1: Status: 0x80408401, Cause: 0x00008000, 
env->hflags: 0x00000000
save_cpu_state():ctx->hflags 00000004 ctx->saved_hflags 00000004
** Interrupt handler called...
** Start of op_eret(): env->hflags 0x00000204 Status 0x80408403
** End of op_eret(): env->hflags 0x00000200 Status 0x80408401
save_cpu_state():ctx->hflags 00000004 ctx->saved_hflags 00000004
save_cpu_state():ctx->hflags 00000004 ctx->saved_hflags 00000004
save_cpu_state():ctx->hflags 00000004 ctx->saved_hflags 00000004
...
MIPS Timer #2: Status: 0x80408401, Cause: 0x00008000, 
env->hflags: 0x00000004
MIPS Timer #3: Status: 0x80408401, Cause: 0x00008000, 
env->hflags: 0x00000004
MIPS Timer #4: Status: 0x80408401, Cause: 0x00008000, 
env->hflags: 0x00000004
MIPS Timer #5: Status: 0x80408401, Cause: 0x00008000, 
env->hflags: 0x00000004
....

             reply	other threads:[~2006-08-16 17:04 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-08-16 17:04 Dirk Behme [this message]
2006-08-16 18:29 ` [Qemu-devel] Wrong reset of MIPS hflags EXL after interrupt? Thiemo Seufer
2006-08-16 20:18   ` Dirk Behme
2006-08-17  6:30     ` Marius Groeger
2006-08-17  6:51       ` Dirk Behme
2006-08-17  7:01         ` Marius Groeger
2006-08-18  8:32   ` Marius Groeger
2006-08-18 10:01     ` Thiemo Seufer

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