Re: [PATCH] Longhaul - Add ignore_latency option

["Rafał Bilski" <rafalbilski@interia.pl>]

[...]
>> So why P_BLK address is valid and have proper lenght?
> 
> One possible scenario is that the same BIOS source runs on
> multiple hardware steppings.  If a broken stepping is found,
> the BIOS writer knows that setting the latency above the
> legal threshold is sufficient to disable the C-state in
> all known ACPI-enabled operating systems, per below.
> 
[...]
>>
>> Why force user to recompilation of distro kernel?
> 
> Why should a distro support this if the BIOS vendor disabled it?
> Is the fact that you have not noticed data corruption a
> sufficient test such that they can suport this?
> 

This is only BIOS that is saying this. Other are saying that this 
combination is C3 capable. What test would be sufficent for You?
Are You aware that don't working C3:
- isn't causing frequency transition,
- will lockup the CPU if there is bus master activity on PCI bus
during transition?

>>> But the real question is why the longhaul driver is checking
>>> for C2 and C3 support in the first place -- as they are not
>>> directly related to the availability of P-states.
>> Because Longhaul isn't using P-states.
> 
> I guess I don't understand what longhaul.c is doing.
> Why is it using ACPI's C2 and C3 register addresses in order
> to do frequency/voltage scaling?
> 

VIA CPU don't like any bus activity during transition (flushing 
caches before isn't enough). If there is change on any pin during PLL 
resync (flush caches or interrupt for example) CPU will be frozen. 
Thanks to ACPI C3 (C2 isn't used) processor have enough time for 
resync. Bus master activity is disabled and will not triger caches 
flush or anything else.

> In the case there those addresses have been deemed invalid for
> the purpose of ACPI C-states, why are they still valid for longhaul?
> 
> -Len
> 

As I explained before this is single case. I don't know any other BIOS 
for mainboard/motherboard with VIA CPU and VIA chipset claiming that 
mobo don't support ACPI C3.

Rafa³


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