From: Mark Lord <liml@rtr.ca>
To: Mark Odell <modell@netezza.com>
Cc: linux-ide@vger.kernel.org
Subject: Re: Cache Coherency in PIO Read/Write
Date: Thu, 31 Aug 2006 14:48:53 -0400 [thread overview]
Message-ID: <44F72F15.40900@rtr.ca> (raw)
In-Reply-To: <4D87F853B8020F4888896B1507DC0F09A2C433@mail2.netezza.com>
Mark Odell wrote:
> For PIO mode transfers, you should not have cache coherency issues since
> the CPU core is doing the read from/write to hardware.
One might think so, but cache lines are tagged with virtual addresses,
so using different virtual addresses (kernel vs. userspace) for the
same data can result in problems like this.
There was a recent thread (this past winter, I believe) devoted to
trying to resolve this issue in 2.6.xx, but I don't remember the final outcome.
Cheers
next prev parent reply other threads:[~2006-08-31 18:48 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-08-31 17:30 Cache Coherency in PIO Read/Write Mark Odell
2006-08-31 18:48 ` Mark Lord [this message]
2006-08-31 19:10 ` Matt Reimer
-- strict thread matches above, loose matches on Subject: below --
2006-08-31 17:02 Fajun Chen
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