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From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: Rodolfo Giometti <giometti@linux.it>,
	linux-mips@linux-mips.org, rmk+serial@arm.linux.org.uk
Subject: Re: [PATCH] au1x00 serial real interrupt
Date: Tue, 05 Sep 2006 19:19:35 +0400	[thread overview]
Message-ID: <44FD9587.3030708@ru.mvista.com> (raw)
In-Reply-To: <20060522165244.GA16223@enneenne.com>

Hello.

Rodolfo Giometti wrote:

> Here my patch to enable real interrupts management for the au1x00
> CPUs.

> ------------------------------------------------------------------------
> 
> diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
> index 7b23664..0197062 100644
> --- a/include/asm-mips/serial.h
> +++ b/include/asm-mips/serial.h
> @@ -11,6 +11,14 @@
>  
>  #include <linux/config.h>
>  
> +#ifdef CONFIG_SOC_AU1X00
> +/*
> + * We have to redefine "is_real_interrupt()" for Au1x00 CPUs...
> + */
> +#undef is_real_interrupt
> +#define is_real_interrupt(irq)	((irq) != ~0)
> +#endif
> +
>  /*
>   * This assumes you have a 1.8432 MHz clock for your UART.
>   *

    Ralf, how about this patch? Can it be applied, at least 3 months after 
posting? Alchemy UART0 uses IRQ0 and 0 is treated as "no IRQ" by 
drivers/serial/8250.c which says the macro should be redefined in 
<asm/serial.h> if needed.

WBR, Sergei

  reply	other threads:[~2006-09-05 15:17 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-05-22 16:52 [PATCH] au1x00 serial real interrupt Rodolfo Giometti
2006-09-05 15:19 ` Sergei Shtylyov [this message]
2006-09-09 16:34   ` Sergei Shtylyov
2006-09-09 16:39     ` Russell King
2006-09-09 16:58       ` Sergei Shtylyov
2006-09-14 18:10       ` Ralf Baechle
2006-09-18 20:13     ` Sergei Shtylyov

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