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charset="us-ascii"; Format="flowed" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" A few comments to take care of before submitting the changes. Reviewed-by: Lijo Lazar On 7/1/2021 3:27 PM, YuBiao Wang wrote: > [Why] > GPU timing counters are read via KIQ under sriov, which will introduce > a delay. > > [How] > It could be directly read by MMIO. > > v2: Add additional check to prevent carryover issue. > v3: Only check for carryover for once to prevent performance issue. > v4: Add comments of the rough frequency where carryover happens. > v5: Remove mutex and gfxoff ctrl unused with current timing registers. > > Signed-off-by: YuBiao Wang > Acked-by: Horace Chen > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 19 ++++++++++++------- > 1 file changed, 12 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index ff7e9f49040e..5f4eae9c9526 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -7609,10 +7609,8 @@ static int gfx_v10_0_soft_reset(void *handle) > > static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) > { > - uint64_t clock; > + uint64_t clock, clock_lo, clock_hi, hi_check; > > - amdgpu_gfx_off_ctrl(adev, false); > - mutex_lock(&adev->gfx.gpu_clock_mutex); > switch (adev->asic_type) { > case CHIP_VANGOGH: > case CHIP_YELLOW_CARP: > @@ -7620,12 +7618,19 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) > ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL); > break; > default: > - clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | > - ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); > + clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); > + clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); > + hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); > + /* The GFX clock frequency is 100MHz, which sets 32-bit carry over > + * roughly every 42 seconds. > + */ SMUIO TSC is not ticking based on GFX clock frequency, it's running at a fixed SMUIO TSC Clock frequency which is 100MHz (second part is right). Replace GFX Clock with SMUIO TSC Clock. > + if (hi_check != clock_hi) { > + clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); > + clock_hi = hi_check; > + } > + clock = (uint64_t)clock_lo | ((uint64_t)clock_hi << 32ULL); These types are already uint64_t and looks cleaner without the cast. Thanks, Lijo > break; > } > - mutex_unlock(&adev->gfx.gpu_clock_mutex); > - amdgpu_gfx_off_ctrl(adev, true); > return clock; > } > > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx