Re: [PATCH v7 3/4] xen/riscv: panic if the device tree advertises neither Svade nor Svadu

[Jan Beulich <jbeulich@suse.com>]

On 16.10.2026 17:34, Baptiste Le Duc wrote:
> p2m_set_pte_flags() presets the A/D bits of G-stage PTEs only when
> RISCV_ISA_EXT_svade is set, which is correct only if the device tree is.
> 
> The privileged spec allows exactly two schemes for updating the PTE A and D
> bits: hardware sets them on access and on write, or accessing a page whose
> A and/or D bit is clear raises a page fault so that software can set them
> (ratified as Svade). Every implementation uses one of them, but platforms
> designed before Svade and Svadu were ratified, such as the HiFive Premier
> P550, may advertise neither. Xen then cannot tell which scheme is in
> effect, so rather than guess, panic in riscv_fill_hwcap() when the device
> tree advertises neither Svade nor Svadu, so that the device tree gets
> fixed.
> 
> Add Svadu to the known ISA extensions so it can be told apart from Svade.
> The comment above the enum asks for new extensions to go at the bottom to
> avoid shuffling, a leftover from Linux where the IDs were macros with
> explicit values. Nothing depends on the enum values, so have the comment
> say that multi-letter extensions follow the order of riscv_isa_ext[].
> 
> Suggested-by: Jan Beulich <jbeulich@suse.com>

Did I, really? Iirc I left open whether to go the panic() route or the
alternative one. Based on Andrew's clarification as to pre-Svad{e,u}
behavior, I think I further tried to indicate that synthesizing the
correct extension may be preferable, to allow older systems' DTs to be
used as-is. In any event ...

> @@ -674,6 +675,22 @@ void __init riscv_fill_hwcap(void)
>                 "Zihintpause unavailable: cpu_relax() gives the CPU no hint; "
>                 "wire up this platform's pause equivalent in cpu_relax()\n");
>  
> +    /*
> +     * The privileged spec allows exactly two schemes for updating the PTE A
> +     * and D bits:
> +     *  1) hardware sets them on access and on write;
> +     *  2) accessing a page whose A and/or D bit is clear raises a page fault,
> +     *     so that software can set them (ratified as Svade).
> +     *
> +     * Every implementation uses one of them, but may predate the extensions
> +     * and advertise neither. The device tree is then ambiguous: Xen cannot
> +     * tell which scheme is in effect, so panic and have the device tree
> +     * fixed.
> +     */
> +    if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svade) &&
> +         !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svadu) )
> +        panic("Device tree advertises neither Svade nor Svadu, A/D bits update scheme unknown\n");

... this message leaves the observer to figure out what to do about the
situation.

Jan