From: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
To: linux-ia64@vger.kernel.org
Subject: Re: [patch] MCA recovery: Montecito support
Date: Thu, 26 Oct 2006 00:21:34 +0000 [thread overview]
Message-ID: <453FFF8E.7040600@jp.fujitsu.com> (raw)
In-Reply-To: <200610201555.k9KFtnvu20317790@clink.americas.sgi.com>
Russ Anderson wrote:
> I reworked that routine to look at all the valid cache target identifiers
> and use the one with the lowest cache level.
>
> I've opened a Quad issue to get clarification from Intel as to
> which target identifier triggered the MCA if there are multiple
> cache checks with valid target identifiers.
>
> This patch also leaves mca.c unchanged. I'll treat that as a seperate
> patch if needed.
Looks good.
But I have one more question (for intel possibly):
- If identifiers in cache_check and bus_check are different,
the cache's always takes priority and the bus's will be ignored.
Are there any opposite case, such as a case of error log that have
corrected cache_checks with ignorable identifiers and an uncorrected
bus_check with significant identifier?
I guess if both are significant it would be separated double MCA,
or should be reset by SAL/platform.
Thanks,
H.Seto
next prev parent reply other threads:[~2006-10-26 0:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-10-20 15:55 [patch] MCA recovery: Montecito support Russ Anderson
2006-10-21 5:22 ` Keith Owens
2006-10-23 0:53 ` Hidetoshi Seto
2006-10-23 4:09 ` Russ Anderson
2006-10-25 22:59 ` Russ Anderson
2006-10-26 0:21 ` Hidetoshi Seto [this message]
2006-10-26 23:20 ` Russ Anderson
2006-10-27 0:25 ` Hidetoshi Seto
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