From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/3] drm/i915: wire up gmbus irq handler Date: Wed, 05 Sep 2012 22:29:32 +0100 Message-ID: <453bf0$5kg1cv@azsmga001.ch.intel.com> References: <1346873081-1305-1-git-send-email-daniel.vetter@ffwll.ch> <1346873081-1305-2-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 762739E752 for ; Wed, 5 Sep 2012 14:29:37 -0700 (PDT) In-Reply-To: <1346873081-1305-2-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Wed, 5 Sep 2012 21:24:40 +0200, Daniel Vetter wrote: > Only enables the interrupt and puts a irq handler into place, doesn't > do anything yet. > > Unfortunately there's no gmbus interrupt support for gen2/3 (safe for > pnv, but there the irq is marked as "Test mode"). The basics look good, but the paranoia says I'd like for the interrupt to only be enabled as required. -Chris -- Chris Wilson, Intel Open Source Technology Centre