From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: optimize ilk/snb irq handler Date: Fri, 30 Nov 2012 11:00:12 +0000 Message-ID: <453bf0$6m9dtt@azsmga001.ch.intel.com> References: <1354271090-27192-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 46D1FE6746 for ; Fri, 30 Nov 2012 03:00:59 -0800 (PST) In-Reply-To: <1354271090-27192-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Fri, 30 Nov 2012 11:24:50 +0100, Daniel Vetter wrote: > We only need to read/write the south interrupt register if the > corresponding bit is set in the north master interrupt register. > Noticed while reading our interrupt handling code. > > Same optimization has already been applied on ivb in > > commit 0e43406bcc1868a316eea6012a0a09d992c53521 > Author: Chris Wilson > Date: Wed May 9 21:45:44 2012 +0100 > > drm/i915: Simplify interrupt processing for IvyBridge > > We can take advantage that the PCH_IIR is a subordinate register to > reduce one of the required IIR reads, and that we only need to clear > interrupts handled to reduce the writes. And by simply tidying the code > we can reduce the line count and hopefully make it more readable. > > Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre