Re: [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.

[Nicolas DET <nd@bplan-gmbh.de>]

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Benjamin Herrenschmidt wrote:

>> As said, no option here. I think there is different way to see how works the PIC. However, from a register point of view. There is just critical, main, peripherals, SDMA.
>>
>> Loot at "ICTL Perstat, MainStat, MainStat, CritStat Encoded Register--MBAR + 0x0524"
> 
> You should have your device-tree match your internal numbering. As you
> noticed, the CRIT interrupt and the EXT interrupts are just the same.

As I see, they aren't.
Critical interrupts defines IRQ 0, as well as slice timer0, WakeUp from 
deep-sleep mode (CCS) interrupt, etc..

Where as main is IRQ[1-3] as well as others stuff.

I did implement/change the irqchip, on your request, because in this 
case (IRQ0 -> l2=1, IRQ[13] -> l2=1->3). and the ack/mask bit are the 
same, it makes sense to have the same func called.

> So right now, what you should do is figure out a proper encoding for the
> firmware, and then either fix your device-tree, or do a hack in
> prom_init.c that fixes it up.
> 

I think the OFW has proper encoding, moreover, this encoding was done up 
on your request and opinion.

If you still want to change the Linux interrupt encoding, I will then 
hack prom_init.c and submmit new patches...

Regards,

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