From: "Jan Beulich" <jbeulich@novell.com>
To: Mats Petersson <Mats.Petersson@amd.com>
Cc: xen-devel@lists.xensource.com
Subject: RE: more segment/selector handling woes
Date: Wed, 22 Nov 2006 14:08:26 +0100 [thread overview]
Message-ID: <456459DA.76E4.0078.0@novell.com> (raw)
In-Reply-To: <907625E08839C4409CE5768403633E0B018E174D@sefsexmb1.amd.com>
>> Note the wording 'as if' - this doesn't tell me whether the
>> internal base
>> address field (which gets stored to the vmcb) can indeed be
>> relied upon.
>> But obviously the code would be simpler if that was the case
>> in reality
>> (and then perhaps the documentation could be updated accordingly).
>
>I believe it would contain whatever is in the [GL]DT... It's ignored by
>the processor (treated as zero). So, you'd have to check if it's GS/FS
>or not, and then use either 0 or [fg]s.base accordingly.
Can you verify this with you hardware guys? It would mean that I'd
also have to change the implementation of get_segment_base()
that I introduced with a patch yesterday.
>Note that one bit in EFER also allows limits for 64-bit segments, but I
>think it's only ever used by VMWare, so it's probably OK to ignore the
>limits completely (in 64-bit mode at least).
Is this being detailed anywhere? Namely, whether there's a CPUID
feature flag for this (or is it always available), and how one would
obtain 64-bit wide limits? I merely can see the flag being defined in
the NPT BIOS And Kernel Developer's Guide (the public
Programmer's Manual doesn't even know this).
Jan
next prev parent reply other threads:[~2006-11-22 13:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-11-22 10:43 more segment/selector handling woes Jan Beulich
2006-11-22 11:31 ` Petersson, Mats
2006-11-22 11:45 ` Jan Beulich
2006-11-22 12:09 ` Petersson, Mats
2006-11-22 12:43 ` Petersson, Mats
2006-11-22 13:08 ` Jan Beulich [this message]
2006-11-22 13:36 ` Petersson, Mats
2006-11-23 13:06 ` Petersson, Mats
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