From: Aurelien Jarno <aurelien@aurel32.net>
To: Alexander Voropay <alec@nwpi.ru>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [RFC] IRQ acknowledge on MIPS
Date: Tue, 23 Jan 2007 17:36:05 +0100 [thread overview]
Message-ID: <45B63975.5020606@aurel32.net> (raw)
In-Reply-To: <00f801c73f03$0b552650$e90d11ac@spb.in.rosprint.ru>
Alexander Voropay a écrit :
> "Aurelien Jarno" <aurelien@aurel32.net> wrote:
>
>> Then after playing with the current code, I am sure we are missing a
>> simple interrupt controller for the MIPS CPU. It supports 6 hardware
>> interrupts (IP2 to IP7) and we are using two of them in the current
>> emulation: one for the i8259a and the other for the timer. In both case
>> the current code assert and deassert a CPU_INTERRUPT_HARD.
>
> The Galileo GT64xxx chip contains an interrupt controller too (for DMA
> cycle indication, built-in Timers e.t.c.). All this interrupt controllers are
> daisy-chained: i8259(as part of the PIIX + PCI), GT64xxx and MIPS internal.
>
Yes, but this controller is not used on the Malta board.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
next prev parent reply other threads:[~2007-01-23 16:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-01-23 0:48 [Qemu-devel] [RFC] IRQ acknowledge on MIPS Aurelien Jarno
2007-01-23 9:01 ` Aurelien Jarno
2007-01-23 15:27 ` Alexander Voropay
2007-01-23 15:40 ` Paul Brook
2007-01-23 20:22 ` Fabrice Bellard
2007-01-23 16:36 ` Aurelien Jarno [this message]
2007-01-23 9:06 ` Marius Groeger
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