From: Jeff Garzik <jeff@garzik.org>
To: Alan <alan@lxorguk.ukuu.org.uk>
Cc: Fajun Chen <fajunchen@gmail.com>,
"linux-ide@vger.kernel.org" <linux-ide@vger.kernel.org>,
Tejun Heo <htejun@gmail.com>
Subject: Re: Question about PATA Sil680 Cache Line Size and Performance Degradation on ARM XScale
Date: Thu, 22 Feb 2007 13:18:16 -0500 [thread overview]
Message-ID: <45DDDE68.8070609@garzik.org> (raw)
In-Reply-To: <20070222185202.03121afc@lxorguk.ukuu.org.uk>
Alan wrote:
>> Since Sil3124 has better PCI read/write performance, as a reference,
>> could someone explain or point me to the PCI configuration code for
>> Sil3124? I couldn't find it in sata_sil24.c.
>
> Are you sure the values used are not the power on ones in this case ?
The values used, most likely, are BIOS-programmed.
sata_sil24.c does not call pci_set_mwi(), which is the only code in the
kernel (besides driver-specific, hand-coded stuff) that adjusts the PCI
cacheline register value.
Jeff
next prev parent reply other threads:[~2007-02-22 18:18 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-02-21 22:56 Question about PATA Sil680 Cache Line Size and Performance Degradation on ARM XScale Fajun Chen
2007-02-22 0:04 ` Alan
2007-02-22 1:21 ` Fajun Chen
2007-02-22 18:52 ` Alan
2007-02-22 18:18 ` Jeff Garzik [this message]
2007-02-22 23:14 ` Fajun Chen
2007-02-22 23:23 ` Jeff Garzik
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