Re: [Qemu-devel] Re: Qemu PPC ethernet checksum bug [PATCH]

[Jason Wessel <jason.wessel@windriver.com>]

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Attached is a patch as well as an example program, where I took the code 
from the from the linux kernel and made a call in with a dummy packet.

It appears the problem is the addic translation does not correctly 
set/reset the carry bit, and this is a regression vs the source base on 
3/7/2007.  With the change here, I can boot the ppc-prep machine again 
and use ethernet.

If you would like a pre-compiled binary of the test case, let me know 
because it was too big to send to the list.

signed-off-by: jason.wessel@windriver.com

Jason.

J. Mayer wrote:
> Hi,
>
> My concern is I cannot reproduce your problem for the following reasons:
> - the PREP machine (and the heathrow too...) is broken and cannot even
> boot. PCI and/or IRQ are broken, so the Linux kernel hangs.
> - when using the "known to work" Linux distributions on the mac99
> machine (please take a look at the STATUS file), I am able to download a
> kernel from www.kernel.org, which makes me think TCP packets are sent
> and received correctly, with valid checksums.
>
> Then, it would be a great thing if you could isolate the failing routine
> and, for example, make a test case usable with linux-user emulation.
> This would be a great help to solve this issue.
>
> Thanks by advance.
>
>   


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Index: qemu/target-ppc/translate.c
===================================================================
--- qemu.orig/target-ppc/translate.c
+++ qemu/target-ppc/translate.c
@@ -772,16 +772,14 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x0
     target_long simm = SIMM(ctx->opcode);
 
     gen_op_load_gpr_T0(rA(ctx->opcode));
-    if (likely(simm != 0)) {
-        gen_op_move_T2_T0();
-        gen_op_addi(simm);
+    gen_op_move_T2_T0();
+    gen_op_addi(simm);
 #if defined(TARGET_PPC64)
-        if (ctx->sf_mode)
-            gen_op_check_addc_64();
-        else
+    if (ctx->sf_mode)
+        gen_op_check_addc_64();
+    else
 #endif
-            gen_op_check_addc();
-    }
+        gen_op_check_addc();
     gen_op_store_T0_gpr(rD(ctx->opcode));
 }
 /* addic. */

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