From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HVHoP-0005ql-El for qemu-devel@nongnu.org; Sat, 24 Mar 2007 21:46:25 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HVHoN-0005qY-0n for qemu-devel@nongnu.org; Sat, 24 Mar 2007 21:46:24 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HVHoM-0005qV-SF for qemu-devel@nongnu.org; Sat, 24 Mar 2007 20:46:22 -0500 Received: from farad.aurel32.net ([82.232.2.251] helo=mail.aurel32.net) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HVHmG-0008Br-Ce for qemu-devel@nongnu.org; Sat, 24 Mar 2007 21:44:13 -0400 Received: from [2001:618:400:fc13:740d:85ff:fef2:5037] (helo=volta.aurel32.net) by mail.aurel32.net with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1HVHlN-00011z-6S for qemu-devel@nongnu.org; Sun, 25 Mar 2007 03:43:17 +0200 Received: from localhost ([127.0.0.1] ident=aurel32) by volta.aurel32.net with esmtp (Exim 4.63) (envelope-from ) id 1HVHlN-0004pV-1d for qemu-devel@nongnu.org; Sun, 25 Mar 2007 03:43:17 +0200 Message-ID: <4605D3B4.4000402@aurel32.net> Date: Sun, 25 Mar 2007 03:43:16 +0200 From: Aurelien Jarno MIME-Version: 1.0 Subject: Re: [Qemu-devel] [Bug] [Patch] MIPS code fails at branch instruction References: <45FB245C.2010900@mail.berlios.de> <20070317143106.GF25863@networkno.de> <45FC3A07.3070302@weilnetz.de> <200703172032.52010.paul@codesourcery.com> <45FEFAC0.4060901@mail.berlios.de> <20070319213445.GJ28895@networkno.de> <20070319223449.GK28895@networkno.de> <4600277F.6070804@mail.berlios.de> <20070325002234.GA14411@networkno.de> In-Reply-To: <20070325002234.GA14411@networkno.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Thiemo Seufer a écrit : > Stefan Weil wrote: >> Hi, >> >> here is the patch which adds a "4KEcR1" CPU (a 4KEc, processor revision 2.2, >> with MIPS32 Release 1 (!) instruction set is the heart of the AR7 SoC). >> >> See also include/asm-mips/cpu.h in the Linux kernel sources: >> ./include/asm-mips/cpu.h:#define PRID_IMP_4KEC 0x8400 >> ./include/asm-mips/cpu.h:#define PRID_IMP_4KECR2 0x9000 > > This was the bit which prompted to to ask The People Who Know[TM]. > Indeed the early 4KEc were MIPS32R1 only. About the branch-in-delay-slot > I got the following information: > > Very simple pipelines with branch delay slots tend to behave like this > (when both branches are taken): > > - Execute the first branch, that is, calculate the target of the > branch. This has no effect until it ran far enough through the > pipeline. Increment PC. > - Execute the second branch. This changes the branch target value > again. Increment PC. > - Execute the second branch's delay slot instruction. Increment PC. > - Now the PC is overridden by the first branch's target. A single > instruction from that place is executed. > - The PC is overridden again by the second branch's target. Normal > execution resumes from there. > > Apparently the SPARC architecture _requires_ this behaviour for all > CPUs. Yep I confirm that, it is clearly explained starting at the page 54 of the SPARC v8 manual. To avoid this behaviour it is possible to cancel the delay slot instruction by having a=1. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net