From: Mike Habeck <habeck@sgi.com>
To: linux-ia64@vger.kernel.org
Subject: Re: [PATCH] SGI Altix : fix pcibr_dmamap_ate32() bug
Date: Fri, 06 Apr 2007 18:53:59 +0000 [thread overview]
Message-ID: <46169747.BC2CB260@sgi.com> (raw)
In-Reply-To: <20070406170439.24071.57637.75833@attica.americas.sgi.com>
"Luck, Tony" wrote:
>
> Can you explain this part of the patch?
>
> -#define PCI32_ATE_CO (0x1 << 1)
> -#define PCI32_ATE_PREC (0x1 << 2)
> +#define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */
> +#define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */
>
> Why is PCI32_ATE_PIO now the same value as PCI_ATE_CO?
The ATE (Address Translation Entry for 32bit PCI mappings) Attribute
bits are different for our PIC Bridge ASIC and our TIOCP Bridge ASIC.
On our PIC Bridge ASIC bit#1 is the `Coherent Translation' attribute,
but on our TIOCP Bridge ASIC bit#1 is the `PIO' attribute
-mike
prev parent reply other threads:[~2007-04-06 18:53 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-04-06 17:04 [PATCH] SGI Altix : fix pcibr_dmamap_ate32() bug Mike Habeck
2007-04-06 17:16 ` Luck, Tony
2007-04-06 18:53 ` Mike Habeck [this message]
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