From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/clflush: fixup handling of cache_dirty
Date: Wed, 27 Oct 2021 13:21:14 +0200 [thread overview]
Message-ID: <46183835-ace2-90d1-dc06-72dd94edce3a@linux.intel.com> (raw)
In-Reply-To: <20211021114410.2437099-1-matthew.auld@intel.com>
On 10/21/21 13:44, Matthew Auld wrote:
> In theory if clflush_work_create() somehow fails here, and we don't yet
> have mm.pages populated then we end up resetting cache_dirty, which is
> likely wrong, since that will potentially skip the flush-on-acquire, if
> it was needed.
>
> It looks like intel_user_framebuffer_dirty() can arrive here before the
> pages are populated.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
> index f0435c6feb68..d09365b5eb29 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
> @@ -20,6 +20,7 @@ static void __do_clflush(struct drm_i915_gem_object *obj)
> {
> GEM_BUG_ON(!i915_gem_object_has_pages(obj));
> drm_clflush_sg(obj->mm.pages);
> + obj->cache_dirty = false;
>
I think the guidelines are to avoid updating state in async work if at
all possible, so we need to add this after __do_clflush() in the sync
path and after dma_fence_work_commit() in the async path.
Will that work?
/Thomas
WARNING: multiple messages have this Message-ID (diff)
From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/i915/clflush: fixup handling of cache_dirty
Date: Wed, 27 Oct 2021 13:21:14 +0200 [thread overview]
Message-ID: <46183835-ace2-90d1-dc06-72dd94edce3a@linux.intel.com> (raw)
In-Reply-To: <20211021114410.2437099-1-matthew.auld@intel.com>
On 10/21/21 13:44, Matthew Auld wrote:
> In theory if clflush_work_create() somehow fails here, and we don't yet
> have mm.pages populated then we end up resetting cache_dirty, which is
> likely wrong, since that will potentially skip the flush-on-acquire, if
> it was needed.
>
> It looks like intel_user_framebuffer_dirty() can arrive here before the
> pages are populated.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
> index f0435c6feb68..d09365b5eb29 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
> @@ -20,6 +20,7 @@ static void __do_clflush(struct drm_i915_gem_object *obj)
> {
> GEM_BUG_ON(!i915_gem_object_has_pages(obj));
> drm_clflush_sg(obj->mm.pages);
> + obj->cache_dirty = false;
>
I think the guidelines are to avoid updating state in async work if at
all possible, so we need to add this after __do_clflush() in the sync
path and after dma_fence_work_commit() in the async path.
Will that work?
/Thomas
next prev parent reply other threads:[~2021-10-27 11:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-21 11:44 [Intel-gfx] [PATCH 1/4] drm/i915/clflush: fixup handling of cache_dirty Matthew Auld
2021-10-21 11:44 ` Matthew Auld
2021-10-21 11:44 ` [Intel-gfx] [PATCH 2/4] drm/i915/clflush: disallow on discrete Matthew Auld
2021-10-21 11:44 ` Matthew Auld
2021-10-27 11:23 ` [Intel-gfx] " Thomas Hellström
2021-10-27 11:23 ` Thomas Hellström
2021-10-21 11:44 ` [Intel-gfx] [PATCH 3/4] drm/i915: move cpu_write_needs_clflush Matthew Auld
2021-10-21 11:44 ` Matthew Auld
2021-10-27 11:29 ` [Intel-gfx] " Thomas Hellström
2021-10-27 11:29 ` Thomas Hellström
2021-10-21 11:44 ` [Intel-gfx] [PATCH 4/4] drm/i915: stop setting cache_dirty on discrete Matthew Auld
2021-10-21 11:44 ` Matthew Auld
2021-10-27 11:30 ` [Intel-gfx] " Thomas Hellström
2021-10-27 11:30 ` Thomas Hellström
2021-10-21 14:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/clflush: fixup handling of cache_dirty Patchwork
2021-10-21 14:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-21 14:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-21 17:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-27 11:21 ` Thomas Hellström [this message]
2021-10-27 11:21 ` [PATCH 1/4] " Thomas Hellström
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