From mboxrd@z Thu Jan  1 00:00:00 1970
From: "H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [PATCH 0/4] i386 - pte update optimizations
Date: Thu, 12 Apr 2007 18:25:05 -0700
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References: <200704120530.l3C5UGbv022814@zach-dev.vmware.com>
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To: Zachary Amsden <zach@vmware.com>
Cc: Andrew Morton <akpm@osdl.org>, Andi Kleen <ak@muc.de>, Virtualization Mailing List <virtualization@lists.osdl.org>, Chris Wright <chrisw@sous-sol.org>, David Rientjes <rientjes@google.com>, Hugh Dickins <hugh@veritas.com>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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Zachary Amsden wrote:
> Some PTE optimizations for native and paravirt-ops kernels; this
> provides a huge win for shadow mode hypervisors and gets rid of
> some unnecessary atomic instructions in native kernels, saving
> even more on UP by getting rid of implicit LOCK on xchg instruction.

You do know that P6 and higher don't do locked bus references as long as =

the value is in the cache, right?

	-hpa

From mboxrd@z Thu Jan  1 00:00:00 1970
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Date: Thu, 12 Apr 2007 18:25:05 -0700
From: "H. Peter Anvin" <hpa@zytor.com>
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To: Zachary Amsden <zach@vmware.com>
CC: Andrew Morton <akpm@osdl.org>, Andi Kleen <ak@muc.de>,
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Subject: Re: [PATCH 0/4] i386 - pte update optimizations
References: <200704120530.l3C5UGbv022814@zach-dev.vmware.com>
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Zachary Amsden wrote:
> Some PTE optimizations for native and paravirt-ops kernels; this
> provides a huge win for shadow mode hypervisors and gets rid of
> some unnecessary atomic instructions in native kernels, saving
> even more on UP by getting rid of implicit LOCK on xchg instruction.

You do know that P6 and higher don't do locked bus references as long as 
the value is in the cache, right?

	-hpa