Re: [PATCH] Xilinx framebuffer device driver

[Andrei Konovalov <akonovalov@ru.mvista.com>]

Grant Likely wrote:
> On 4/24/07, Andrei Konovalov <akonovalov@ru.mvista.com> wrote:
>> Add support for the video controller IP block included into Xilinx 
>> ML300 and
>> ML403 reference designs.
>>
>> Signed-off-by: Andrei Konovalov <akonovalov@ru.mvista.com>
>> ---
>>
>> This patch relies on the "Patchset to establish sanity in Xilinx 
>> Virtex support" by Gran Likely to have
>> the frame buffer device registered on the platform bus. Without this 
>> patchset one needs to fill in
>> the struct platform_device and make sure platform_device_register() is 
>> called elsewhere.
>>
>> Reviews and comments are welcome.
>>
>> Would be nice to get this driver into mainline for the 2.6.22.
> 
> Quick comment on first perusal:  The driver uses the out_be32 macro
> directly for accessing registers, which doesn't work if the FB block
> is configured for DCR access (like the ML403 reference design).

Yes, that's true.
But (at least) the EDK 8.1 reference design for ML403 has also opb2dcr bridge.
That's why I've tested the patch without problems on ML403 (in addition
to ML300).

I'll add DCR access, but not sure if I need a separate bitstream to
test DCR access (could I access the DCR registers directly in presence
of the bridge or not).

> There will need to be a property in the platform device binding to determine
> how to access registers.

OK.
The only problem is that there is no indication in the xparameters.h of how the
registers should be accessed (via DCR or opb).
Let's suppose XPAR_TFT_0_USE_DCR would be added by EDK (like XPAR_XINTC_USE_DCR
is used for the interrupt controller).

> Cheers,
> g.
> 

Thanks,
Andrei