From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Hk4ki-0005Wk-Qj for qemu-devel@nongnu.org; Fri, 04 May 2007 16:51:44 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Hk4kg-0005Ol-Q7 for qemu-devel@nongnu.org; Fri, 04 May 2007 16:51:44 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Hk4kg-0005OY-Lw for qemu-devel@nongnu.org; Fri, 04 May 2007 16:51:42 -0400 Received: from moutng.kundenserver.de ([212.227.126.177]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Hk4e0-0001qp-Et for qemu-devel@nongnu.org; Fri, 04 May 2007 16:44:48 -0400 Message-ID: <463B9B3C.8050103@mail.berlios.de> Date: Fri, 04 May 2007 22:44:44 +0200 From: Stefan Weil MIME-Version: 1.0 Subject: Re: [Qemu-devel] [BUG] QEMU crash during cpu reset (MIPS regression) References: <463B939A.1090508@mail.berlios.de> <200705042127.21769.paul@codesourcery.com> In-Reply-To: <200705042127.21769.paul@codesourcery.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU Developers Paul Brook schrieb: >> We can either re-arrange the entries in CPUMIPSState >> (move those which must not be zero'ed to the end), or >> cpu_reset must call cpu_mips_register. >> >> Which solution is better? > > ARM uses the latter solution. > IMHO it's better to do that than try and extend the hacks were some > fields are > left untouched by a reset. > > Paul > I had just implemented this 2nd solution. It was not sufficient because env->irq was also zero'ed, so Linux starts after reset without the MIPS timer interrupt which is not good :-). Re-arranging env->irq is not a nice solution but it helped. Stefan