From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02E82C61DE2 for ; Mon, 31 Aug 2026 11:14:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0zy0-0003Jk-T2; Mon, 31 Aug 2026 07:14:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0zxz-0003E6-Jg for qemu-arm@nongnu.org; Mon, 31 Aug 2026 07:14:19 -0400 Received: from smtpout9.mo540.mail-out.ovh.net ([51.210.91.58]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0zxs-0003ec-AO for qemu-arm@nongnu.org; Mon, 31 Aug 2026 07:14:18 -0400 Received: from director1.derp.mail-out.ovh.net (director1.derp.mail-out.ovh.net [79.137.60.221]) by mo540.mail-out.ovh.net (Postfix) with ESMTPS id 4hYRFr4Qd1z44lM; Mon, 31 Aug 2026 11:14:08 +0000 (UTC) Received: from director1.derp.mail-out.ovh.net (director1.derp.mail-out.ovh.net. [127.0.0.1]) by director1.derp.mail-out.ovh.net (inspect_sender_mail_agent) with SMTP for ; Mon, 31 Aug 2026 11:14:07 +0000 (UTC) Received: from mta11.priv.ovhmail-u2.ea.mail.ovh.net (unknown [10.110.58.168]) by director1.derp.mail-out.ovh.net (Postfix) with ESMTPS id 4hYRFq6snnz6GrT; Mon, 31 Aug 2026 11:14:07 +0000 (UTC) Received: from kaod.org (unknown [10.1.6.3]) (Authenticated sender: clg@kaod.org) by mta11.priv.ovhmail-u2.ea.mail.ovh.net (Postfix) with ESMTPSA id A4DFA2403FCF; Mon, 31 Aug 2026 11:14:06 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-106R0067c340bd9-e64f-47f1-8006-12aba91b76da, 20713A92955D5A277E4AF24F7FE8A47CC1774BFC) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 Message-ID: <463ed44f-4f40-4e49-9dae-e4f1f2ef721b@kaod.org> Date: Mon, 31 Aug 2026 13:14:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/2] hw/misc/aspeed_sbc: Derive secure boot state from OTP config straps To: Kane Chen , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" Cc: Troy Lee References: <20260831053658.462203-1-kane_chen@aspeedtech.com> <20260831053658.462203-3-kane_chen@aspeedtech.com> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Content-Language: en-US, fr Autocrypt: addr=clg@kaod.org; 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v=1; b=oKRPbDk93bi3iJE0OVsmOtzvSSaWM2taS2JpDNPtjeA7FtvCcI8gv55Tu/p4a0qzoAonb1bD Y+TYSkc0hBL8DGFzeb6IZLwXDWx618oXB7PqE/DLPoBHFyS33n0rhK2dC93wNycTL//BYCLsdFo N0FfivvGvB6WzoUixfr/ZyiUV9VW9DmI7nbfDNDoq0+zEj0f5Mksw7IqldZ+YMTiEREIcE+FN8Y cQfteOxfSz+BJY00l3GN/E091Xb3ddygmwaF1Ot/9TU9WDPI+KabY7AF9qcKWWDwHDEcHYkksWy GPCWc6iCHIhk4dxuIQurlvzMjG/XnFDTxm7Nt348V+iCA== Received-SPF: pass client-ip=51.210.91.58; envelope-from=clg@kaod.org; helo=smtpout9.mo540.mail-out.ovh.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 8/31/26 07:37, Kane Chen wrote: > The secure boot enable bit in R_STATUS and the R_QSR signing settings > were both driven by a fixed "signing-settings" machine property, but > the two ended up inconsistent: the logic guarding the R_STATUS enable > bit was broken and never actually set it, while R_QSR still reported > the configured signing settings, so a machine could show secure boot > configured in R_QSR while R_STATUS said it was disabled. > > Instead of relying on the property, read the relevant OTP > configuration bits directly and derive both the R_STATUS secure boot > enable state and the QSR value from them, matching how the real > hardware determines these settings. The now-unused "signing-settings" > property is removed. > > Signed-off-by: Kane-Chen-AS > --- > include/hw/misc/aspeed_sbc.h | 2 -- > hw/misc/aspeed_sbc.c | 34 ++++++++++++++++++++++++---------- > 2 files changed, 24 insertions(+), 12 deletions(-) > > diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h > index 7152497b2a..474922cbd2 100644 > --- a/include/hw/misc/aspeed_sbc.h > +++ b/include/hw/misc/aspeed_sbc.h > @@ -32,8 +32,6 @@ OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC) > struct AspeedSBCState { > SysBusDevice parent; > > - uint32_t signing_settings; > - > MemoryRegion iomem; > > uint32_t regs[ASPEED_SBC_NR_REGS]; > diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c > index 5d4da39d30..ce03f717a9 100644 > --- a/hw/misc/aspeed_sbc.c > +++ b/hw/misc/aspeed_sbc.c > @@ -63,6 +63,19 @@ > /* OTP Address */ > #define OTP_CFG0 (0x800) > > +static bool aspeed_sbc_otp_read(AspeedSBCState *s, uint32_t otp_addr); > + > +static uint32_t aspeed_otp_read_cfg0(AspeedSBCState *s) > +{ > + uint32_t value = 0; > + > + if (aspeed_sbc_otp_read(s, OTP_CFG0)) { This call is clobbering s->regs[R_CAMP1]. Let's see how we can improve patch 1 first. Thanks, C. > + value = s->regs[R_CAMP1]; > + } >> + return value;> +} > + > static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size) > { > AspeedSBCState *s = ASPEED_SBC(opaque); > @@ -76,7 +89,12 @@ static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size) > return 0; > } > > - return s->regs[addr]; > + switch (addr) { > + case R_QSR: > + return aspeed_otp_read_cfg0(s); > + default: > + return s->regs[addr]; > + } > } > > static bool aspeed_sbc_otp_read(AspeedSBCState *s, > @@ -291,6 +309,7 @@ static bool aspeed_get_abr_state(AspeedSBCState *s) > static void aspeed_sbc_reset_hold(Object *obj, ResetType type) > { > AspeedSBCState *s = ASPEED_SBC(obj); > + uint32_t value; > bool abr; > > memset(s->regs, 0, sizeof(s->regs)); > @@ -304,11 +323,11 @@ static void aspeed_sbc_reset_hold(Object *obj, ResetType type) > s->regs[R_STATUS] |= ABR_EN; > } > > - if (s->signing_settings) { > - s->regs[R_STATUS] &= SECURE_BOOT_EN; > - } > + value = aspeed_otp_read_cfg0(s); > > - s->regs[R_QSR] = s->signing_settings; > + if (value & BIT(1)) { > + s->regs[R_STATUS] |= SECURE_BOOT_EN; > + } > } > > static void aspeed_sbc_instance_init(Object *obj) > @@ -352,10 +371,6 @@ static const VMStateDescription vmstate_aspeed_sbc = { > } > }; > > -static const Property aspeed_sbc_properties[] = { > - DEFINE_PROP_UINT32("signing-settings", AspeedSBCState, signing_settings, 0), > -}; > - > static void aspeed_sbc_class_init(ObjectClass *klass, const void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > @@ -364,7 +379,6 @@ static void aspeed_sbc_class_init(ObjectClass *klass, const void *data) > dc->realize = aspeed_sbc_realize; > rc->phases.hold = aspeed_sbc_reset_hold; > dc->vmsd = &vmstate_aspeed_sbc; > - device_class_set_props(dc, aspeed_sbc_properties); > } > >