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Date: Tue, 08 May 2007 10:34:37 -0700
From: Dave Jiang <djiang@mvista.com>
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To: Olof Johansson <olof@lixom.net>
Subject: Re: [PATCH] powerpc: add dts entries to 85xx for EDAC
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Olof Johansson wrote:
> Hi,
> 
>> diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
>> index f261d64..f411bc1 100644
>> --- a/arch/powerpc/boot/dts/mpc8540ads.dts
>> +++ b/arch/powerpc/boot/dts/mpc8540ads.dts
>> @@ -48,6 +48,22 @@
>>  		reg = <e0000000 00100000>;	// CCSRBAR 1M
>>  		bus-frequency = <0>;
>>  
>> +		memory-controller@2000 {
>> +			compatible = "fsl,85xx-memory-controller";
>> +			reg = <2000 1000>;
>> +			interrupt-parent = <&mpic>;
>> +			interrupts = <2 2>;
>> +		};
>> +
>> +		l2-cache-controller@20000 {
>> +			compatible = "fsl,85xx-memory-controller";
> 
> Interesting. Is the programming model really the same for the memory and cache controller?
> 
> 
> -Olof

That's an oops on my part. Thanks for pointing it out.


---

-= Dave =-