Re: [Qemu-devel] [MIPS][PATCH] Fix mfc0 and dmtc0 instructions on MIPS64

[Aurelien Jarno <aurelien@aurel32.net>]

Thiemo Seufer a écrit :
> Aurelien Jarno wrote:
>> Hi all,
>>
>> The patch below fixes the mfc0 and dmtc0 instructions for the 
>> MIPS64 target:
>>
>> - The mfc0 instruction should return the 32 lowest bits of the 
>>   coprocessor 0 register sign extended to 64-bit.
> 
> Agreed, and I think it doess already. (The places where you added
> casts read fron 32bit wide registers anyway.)

Oops, I haven't seen before that those registers were declared as
int32_t, so that the sign extension is already done.

Forget that part.

>> - The mtc0 instruction should do the same as the dmtc0 instruction for 
>>   64-bit coprocessor registers instead of copying only the low 32 bits.
> 
> I'm not entirely sure about this, but it feels wrong, as mtc0 should
> have the same behaviour as on 32bit CPUs. What prompted the change here?

The MIPS64 ISA manual:

Operation:
   data  GPR[rt]
   if (Width(CPR[0,rd,sel]) = 64) then
        CPR[0,rd,sel]  data
   else
        CPR[0,rd,sel]  data31..0
   endif

But it is also need if you need to run a 32-bit kernel on MIPS64. For
example the EntryHi register is a 64-bit register, and the higher 32
bits (and most notably the R part of this register) has to be filled.
This part is initialised when an exception occurs, so even if a 32-bit
kernel don't know about it, it already holds the correct values.

>> - The XContest register does not exists on MIPS32 CPU.
> 
> Indeed, but simply not wiring up the instruction decoding for 32bit
> should be good enough, no need to #ifdef everything.
> 

Ok.

Bye,
Aurelien

-- 
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