From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HnFdk-0007iX-AQ for qemu-devel@nongnu.org; Sun, 13 May 2007 11:05:40 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HnFdh-0007iL-Tt for qemu-devel@nongnu.org; Sun, 13 May 2007 11:05:39 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HnFdh-0007iI-Oe for qemu-devel@nongnu.org; Sun, 13 May 2007 11:05:37 -0400 Received: from farad.aurel32.net ([82.232.2.251] helo=mail.aurel32.net) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HnFW2-0001Sg-Dc for qemu-devel@nongnu.org; Sun, 13 May 2007 10:57:42 -0400 Message-ID: <46472766.5090209@aurel32.net> Date: Sun, 13 May 2007 16:57:42 +0200 From: Aurelien Jarno MIME-Version: 1.0 Subject: Re: [Qemu-devel] [MIPS][PATCH] Fix mfc0 and dmtc0 instructions on MIPS64 References: <20070512144724.GB19249@amd64.aurel32.net> <20070513143749.GB8380@networkno.de> In-Reply-To: <20070513143749.GB8380@networkno.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Thiemo Seufer Thiemo Seufer a écrit : > Aurelien Jarno wrote: >> Hi all, >> >> The patch below fixes the mfc0 and dmtc0 instructions for the >> MIPS64 target: >> >> - The mfc0 instruction should return the 32 lowest bits of the >> coprocessor 0 register sign extended to 64-bit. > > Agreed, and I think it doess already. (The places where you added > casts read fron 32bit wide registers anyway.) Oops, I haven't seen before that those registers were declared as int32_t, so that the sign extension is already done. Forget that part. >> - The mtc0 instruction should do the same as the dmtc0 instruction for >> 64-bit coprocessor registers instead of copying only the low 32 bits. > > I'm not entirely sure about this, but it feels wrong, as mtc0 should > have the same behaviour as on 32bit CPUs. What prompted the change here? The MIPS64 ISA manual: Operation: data GPR[rt] if (Width(CPR[0,rd,sel]) = 64) then CPR[0,rd,sel] data else CPR[0,rd,sel] data31..0 endif But it is also need if you need to run a 32-bit kernel on MIPS64. For example the EntryHi register is a 64-bit register, and the higher 32 bits (and most notably the R part of this register) has to be filled. This part is initialised when an exception occurs, so even if a 32-bit kernel don't know about it, it already holds the correct values. >> - The XContest register does not exists on MIPS32 CPU. > > Indeed, but simply not wiring up the instruction decoding for 32bit > should be good enough, no need to #ifdef everything. > Ok. Bye, Aurelien -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net