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([2a01:e0a:c:37e0:ced3:55bd:f454:e722]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4389046c59csm135571775e9.40.2025.01.20.02.37.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Jan 2025 02:37:27 -0800 (PST) Message-ID: <4648b8d1-98fb-4caa-a443-bc8bb0e9f6cc@redhat.com> Date: Mon, 20 Jan 2025 11:37:26 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/8] drm/ast: Align Gen1 DVO detection to register manual To: Thomas Zimmermann , airlied@redhat.com Cc: dri-devel@lists.freedesktop.org References: <20250117103450.28692-1-tzimmermann@suse.de> <20250117103450.28692-7-tzimmermann@suse.de> From: Jocelyn Falempe In-Reply-To: <20250117103450.28692-7-tzimmermann@suse.de> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: p1InkdbvR2XP8TQbJUvuos9Nzq9W_A8vmxkDjGP0PE8_1737369448 X-Mimecast-Originator: redhat.com Content-Language: en-US, fr Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 17/01/2025 11:29, Thomas Zimmermann wrote: > Align variable names and register constants for TX-chip detection > to the names in the register manual. Thanks, it looks good to me. Reviewed-by: Jocelyn Falempe > > Signed-off-by: Thomas Zimmermann > --- > drivers/gpu/drm/ast/ast_main.c | 6 +++--- > drivers/gpu/drm/ast/ast_reg.h | 1 + > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c > index 50b57bc15d53c..40d3b7770cf18 100644 > --- a/drivers/gpu/drm/ast/ast_main.c > +++ b/drivers/gpu/drm/ast/ast_main.c > @@ -76,7 +76,7 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post) > }; > > struct drm_device *dev = &ast->base; > - u8 jreg, vgacrd1; > + u8 vgacra3, vgacrd1; > > /* > * Several of the listed TX chips are not explicitly supported > @@ -106,8 +106,8 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post) > * SIL164 when there is none. > */ > if (!need_post) { > - jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); > - if (jreg & 0x80) > + vgacra3 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); > + if (vgacra3 & AST_IO_VGACRA3_DVO_ENABLED) > ast->tx_chip = AST_TX_SIL164; > } > } else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) { > diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h > index 2aadf07d135af..0745d58e5b450 100644 > --- a/drivers/gpu/drm/ast/ast_reg.h > +++ b/drivers/gpu/drm/ast/ast_reg.h > @@ -32,6 +32,7 @@ > #define AST_IO_VGACR80_PASSWORD (0xa8) > #define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1) > #define AST_IO_VGACRA1_MMIO_ENABLED BIT(2) > +#define AST_IO_VGACRA3_DVO_ENABLED BIT(7) > #define AST_IO_VGACRB6_HSYNC_OFF BIT(0) > #define AST_IO_VGACRB6_VSYNC_OFF BIT(1) > #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */