[Qemu-devel] [PATCH] floppy support for guest-OS OS9/x86 (aka OS9000)

["W. Tasin" <tasin@fhm.edu>]

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Hello *,

I tried to make OS9/x86 runnable on qemu; with an existing hd image it 
already worked, but w/o floppy support. To make this also available I'd 
a look at the sources and (after some time ...) I was able to solve 3 
little problems.
- boot from floppy didn't work
- floppy support inside os9/x86 didn't work
- a second ide reset sequence didn't work correctly

So here my patches (against snapshot 
http://qemu-forum.ipi.fi/qemu-snapshots/qemu-snapshot-2007-05-18_05.tar.bz2)

You can find a more detailed explanation on 
http://pc01-lsw.ee.fhm.edu/wiki/QEmu/OS9Patch

HTH
Ciao

Walter

PS: Please CC me on questions, 'cause I'm not subscribed to the list.

-- 
Walter Tasin, M.Sc.
Fakultät für Elektrotechnik und Informationstechnik
Fachhochschule München, Munich University of Applied Sciences



[-- Attachment #2: vl.diff --]
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--- vl.h	Wed May  9 20:25:36 2007
+++ vl.h	Thu May 17 09:04:44 2007
@@ -1011,6 +1011,7 @@
 int DMA_write_memory (int nchan, void *buf, int pos, int size);
 void DMA_hold_DREQ (int nchan);
 void DMA_release_DREQ (int nchan);
+void DMA_set_TC (int nchan);
 void DMA_schedule(int nchan);
 void DMA_run (void);
 void DMA_init (int high_page_enable);


[-- Attachment #3: ide.diff --]
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--- hw/ide.c	Wed May  9 20:25:36 2007
+++ hw/ide.c	Thu May 17 22:36:25 2007
@@ -2176,6 +2176,7 @@
                 s->status = 0x00; /* NOTE: READY is _not_ set */
             else
                 s->status = READY_STAT | SEEK_STAT;
+            s->cur_drive = s;
             ide_set_signature(s);
         }
     }


[-- Attachment #4: fdc.diff --]
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--- hw/fdc.c	Sat Apr 14 13:01:32 2007
+++ hw/fdc.c	Wed May 16 17:14:54 2007
@@ -917,7 +920,10 @@
     fdctrl->fifo[6] = FD_SECTOR_SC;
     fdctrl->data_dir = FD_DIR_READ;
     if (fdctrl->state & FD_CTRL_BUSY) {
-        DMA_release_DREQ(fdctrl->dma_chann);
+        if (fdctrl->dma_en) {
+            DMA_release_DREQ(fdctrl->dma_chann);
+            DMA_set_TC(fdctrl->dma_chann);
+        }
         fdctrl->state &= ~FD_CTRL_BUSY;
     }
     fdctrl_set_fifo(fdctrl, 7, 1);


[-- Attachment #5: fdc1.diff --]
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--- hw/fdc.c	Sat Apr 14 13:01:32 2007
+++ hw/fdc.c	Thu May 17 08:54:36 2007
@@ -376,7 +376,8 @@
     uint8_t state;
     uint8_t dma_en;
     uint8_t cur_drv;
-    uint8_t bootsel;
+    uint8_t bootsel;
+    uint8_t first_sense;
     /* Command FIFO */
     uint8_t fifo[FD_SECTOR_LEN];
     uint32_t data_pos;
@@ -596,7 +597,8 @@
     fdctrl->version = 0x90; /* Intel 82078 controller */
     fdctrl->irq = irq;
     fdctrl->dma_chann = dma_chann;
-    fdctrl->io_base = io_base;
+    fdctrl->io_base = io_base;
+    fdctrl->first_sense=0;
     fdctrl->config = 0x60; /* Implicit seek, polling & FIFO enabled */
     if (fdctrl->dma_chann != -1) {
         fdctrl->dma_en = 1;
@@ -651,7 +653,7 @@
 	return;
     }
 #endif
-    if (~(fdctrl->state & FD_CTRL_INTR)) {
+    if (!(fdctrl->state & FD_CTRL_INTR)) {
         qemu_set_irq(fdctrl->irq, 1);
         fdctrl->state |= FD_CTRL_INTR;
     }
@@ -668,6 +670,7 @@
     fdctrl_reset_irq(fdctrl);
     /* Initialise controller */
     fdctrl->cur_drv = 0;
+    fdctrl->first_sense = 4;
     /* FIFO state */
     fdctrl->data_pos = 0;
     fdctrl->data_len = 0;
@@ -1388,27 +1394,35 @@
             /* RECALIBRATE */
             FLOPPY_DPRINTF("RECALIBRATE command\n");
             /* 1 parameter cmd */
-            fdctrl->data_len = 2;
+            fdctrl->data_len = 2;
+            fdctrl->first_sense=0;
             goto enqueue;
         case 0x08:
             /* SENSE_INTERRUPT_STATUS */
             FLOPPY_DPRINTF("SENSE_INTERRUPT_STATUS command (%02x)\n",
-                           fdctrl->int_status);
+                           fdctrl->int_status);
+            uint8_t act_drv = fdctrl->cur_drv;
             /* No parameters cmd: returns status if no interrupt */
-#if 0
+            if (fdctrl->first_sense > 0)
+                act_drv=4-fdctrl->first_sense--;
+
+#if 1
             fdctrl->fifo[0] =
-                fdctrl->int_status | (cur_drv->head << 2) | fdctrl->cur_drv;
+                (fdctrl->state & FD_CTRL_INTR) ? 
+            fdctrl->int_status : 0x80 | (cur_drv->head << 2) | act_drv;
 #else
             /* XXX: int_status handling is broken for read/write
                commands, so we do this hack. It should be suppressed
                ASAP */
             fdctrl->fifo[0] =
-                0x20 | (cur_drv->head << 2) | fdctrl->cur_drv;
+                0x20 | (cur_drv->head << 2) | act_drv ;
 #endif
+
             fdctrl->fifo[1] = cur_drv->track;
-            fdctrl_set_fifo(fdctrl, 2, 0);
-	    fdctrl_reset_irq(fdctrl);
-	    fdctrl->int_status = 0xC0;
+            fdctrl_set_fifo(fdctrl, ((fdctrl->fifo[0] & 0xF0) != 0x80) ? 2 : 1, 0);
+                
+    	     fdctrl_reset_irq(fdctrl);
+            fdctrl->int_status = 0xC0;
             return;
         case 0x0E:
             /* DUMPREG */


[-- Attachment #6: dma.diff --]
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--- hw/dma.c	Mon Nov 21 23:29:56 2005
+++ hw/dma.c	Wed May 16 13:02:30 2007
@@ -311,6 +311,16 @@
     dma_controllers[ncont].status |= 1 << (ichan + 4);
 }
 
+void DMA_set_TC (int nchan)
+{
+    int ncont, ichan;
+
+    ncont = nchan > 3;
+    ichan = nchan & 3;
+    linfo ("tc set cont=%d chan=%d\n", ncont, ichan);
+    dma_controllers[ncont].status |= 1 << ichan;
+}
+
 void DMA_release_DREQ (int nchan)
 {
     int ncont, ichan;