From mboxrd@z Thu Jan 1 00:00:00 1970 From: John Byrne Subject: Re: [RFC][PATCH 0/6] HVM PCI Passthrough (non-IOMMU) Date: Thu, 07 Jun 2007 19:53:28 -0700 Message-ID: <4668C4A8.4000208@hp.com> References: <9392A06CB0FDC847B3A530B3DC174E7B02A95EDA@mse10be1.mse10.exchange.ms> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <9392A06CB0FDC847B3A530B3DC174E7B02A95EDA@mse10be1.mse10.exchange.ms> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Guy Zana Cc: xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org Guy, I tried your patches with a bnx2 NIC on SLES10 and they didn't work. The first reason was that you mask off the capabilities bit in the PCI status. If I got rid of this, I could at least get the NIC to configure, but it didn't work and the dropped packets looked to be random garbage, so I don't think it was talking to the device properly. (But I understand almost nothing about PCI device configuration, so I don't know what to look for.) I haven't noticed the merge tree springing into existence into on xenbits, so is there any progress on making into a real feature? It sounds like most of the work needs to be done between you and Intel, but I could certainly help with testing. One thing I am interested in is, with the 1:1 mapping, could we disable the VT page-fault handling? I've found that the page-fault overhead for VT is horrible and would probably affect fork-exec benchmarks significantly. Thanks, John Byrne