Re: [RFC/PATCH] powerpc: MPC7450 L2 HW cache flush feature utilization

[Vladislav Buzov <vbuzov@ru.mvista.com>]

Benjamin Herrenschmidt wrote:

>>>The erratum says nothing about any HW bugs with L3 cache flush. I just 
>>>mentioned that the L3 cache flush operation described in MPC7450 
>>>Reference manual is similar to the L2 using the L3 cache hardware 
>>>flushing mechanism. For instance, it requires a complete L3 locking 
>>>before flushing.
>>>      
>>>
>>Then I think we should use that mechanism in the Linux kernel.
>>Anything else is waiting for bugs to bite.
>>    
>>
>
>I just figured out ... we actually already have all of that cache flush
>code :-) I wrote most of it in fact. It's just that for some (bad)
>reasons, it's somewhat hidden in arch/powerpc/platforms/powermac/cache.S
>
>So I think best would be to take it from there and make it more
>generic ...
>  
>
I'm just wondering who is supposed to do that. I can copy the code from 
cache.S to l2cr_6xx.S and test it on 7448 since I have only this 
processor on hand. So, I can't test the L3.      

I've looked through cache.S and see it contains a dcbf loop over 4Mb 
along with L2, L3 HW cache flushing. The comments says 'Due to a bug 
with the HW flush on some CPU revs, we occasionally experience data 
corruption...'. Could you please clarify which CPU revisions have this 
bug and whether it is the same bug described in errata and requiring a 
complete cache locking before flushing? Do we still need to use the dcbf 
loop in _set_L2CR() for MPC7450 processors?

Thanks,
Vlad.

>Cheers,
>Ben.
>
>
>  
>