From mboxrd@z Thu Jan 1 00:00:00 1970 From: Robert Hancock Subject: Re: serial flow control appears broken Date: Thu, 02 Aug 2007 10:14:22 -0600 Message-ID: <46B202DE.5000709@shaw.ca> References: <46A84B4A.6070902@shaw.ca> <46A8C6F1.4080309@howardsilvan.com> <46AA2748.80703@howardsilvan.com> <46AA3801.7090204@shaw.ca> <20070728092842.GC26443@flint.arm.linux.org.uk> <46B1F0CB.9060106@rtr.ca> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from shawidc-mo1.cg.shawcable.net ([24.71.223.10]:26110 "EHLO pd3mo1so.prod.shaw.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753612AbXHBQO0 (ORCPT ); Thu, 2 Aug 2007 12:14:26 -0400 In-reply-to: <46B1F0CB.9060106@rtr.ca> Sender: linux-serial-owner@vger.kernel.org List-Id: linux-serial@vger.kernel.org To: Mark Lord Cc: "Maciej W. Rozycki" , Russell King , Lee Howard , linux-serial@vger.kernel.org, tytso@mit.edu, linux-kernel@vger.kernel.org Mark Lord wrote: > I don't believe the speed of the machine has much to do with it, > as IDE PIO is always at pretty much the same speed (or slower) > regardless of the CPU speed. > > Best case is about .120 usec per 16-bit word, but that doesn't often pan > out > in practice. More typical is something closer to 1 usec per 16-bit word. > > So, for multcount=16 (very common), best case is 16 * 256 * .120 = 491 > usec, > plus extra overhead for reading the IDE status register (another usec or > so), > and other stuff. Figure maybe 500usec total per interrupt for multcount=16 > in the best case, or 4000usec in the worst case. > > At 115200bps, we get a byte every 86 usec or so. Assuming the UART FIFO > is set to interrupt (warn) us at 12/16 full, we have 4*86 = 344 usec to > respond and de-assert RTS. Less than that in practice. > > Conclusion: using IDE multisector PIO is not a good idea with high speed > serial transfers happening, since we cannot respond quickly enough. > > It might be possible to set the buffer underrun threshold lower in the > UART (?). > > All that said, I doubt that his system is using IDE PIO in the first place. > Dunno how long IDE DMA interrupts take, but it's probably in the 20-50 > usec range. I think that PIO transfers only have to be done with interrupts disabled on really old, evil controllers (without unmask set). I don't think libata ever disables interrupts during transfers(?) -- Robert Hancock Saskatoon, SK, Canada To email, remove "nospam" from hancockr@nospamshaw.ca Home Page: http://www.roberthancock.com/