From: Tejun Heo <htejun@gmail.com>
To: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Cc: Daniel J Blueman <daniel.blueman@gmail.com>,
Mark Lord <lkml@rtr.ca>,
jgarzik@pobox.com, linux-ide@vger.kernel.org,
Linux Kernel <linux-kernel@vger.kernel.org>
Subject: Re: ICH8 CF timeout (regression)...
Date: Tue, 07 Aug 2007 02:36:14 +0900 [thread overview]
Message-ID: <46B75C0E.8010007@gmail.com> (raw)
In-Reply-To: <20070806102836.ea157fed.kristen.c.accardi@intel.com>
Kristen Carlson Accardi wrote:
> In the data sheet in section 5.15.2.3 it describes a value of map.mv of
> 1 as meaning that the SATA controller is emulating the logical secondary
> channel, and the PATA channel will be the primary. For a value of
> map.mv == 2, we have the SATA controller being primary, and the PATA
> is secondary. So, if I'm understanding the way ata_piix does mapping,
> it seems like for a value of 2, we should have [p0, p2, ide, ide] and
> for a value of 1 we should have [ide, ide, p0, p2] - although for ICH8M
> it seems like 1 should not be a valid value. My reading the ICH8 spec is
> that ICH8M only implements a map value of 2, and 1 should be reserved
> (see section 12.1.33).
Alright, thanks a lot.
--
tejun
prev parent reply other threads:[~2007-08-06 17:36 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-08-02 10:48 ICH8 CF timeout (regression) Daniel J Blueman
2007-08-02 16:59 ` Tejun Heo
2007-08-02 21:11 ` Daniel J Blueman
2007-08-02 22:42 ` Mark Lord
2007-08-03 10:22 ` Daniel J Blueman
2007-08-03 10:41 ` Tejun Heo
2007-08-03 22:38 ` Daniel J Blueman
2007-08-04 6:04 ` Tejun Heo
2007-08-06 17:28 ` Kristen Carlson Accardi
2007-08-06 17:36 ` Tejun Heo [this message]
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