Re: [Xenomai-help] Unexpected switch to secondary mode

[Wolfgang Grandegger <wg@domain.hid>]

Dmitry Adamushko wrote:
> [ forgot to add the list : ]
> 
> ---------- Forwarded message ----------
> 
> On 06/08/07, Philippe Gerum <rpm@xenomai.org> wrote:
>>> [ ... ]
>>> But I have another question: since the nocow patch is platform
>>> independent, why not integrating it in the I-pipe patch for power pc ?
>>>
>> It is merged into the latest patches against the powerpc/ tree.
> 
> [ Mainly, just out of curiosity ]
> 
> I've actually tried 'google'ing for an overview of the MMU on ppc but
> it doesn't seem to be easily
> available on the net.

Unfortunately, there is no common MMU implementation for the PowerPC 
processors. It is usually described in the User Manual for the IBM, 
Freescale or AMCC processor, e.g.:

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5200&fpsp=1&tab=Documentation_Tab

> 
> Do I understand it right that in the PPC arch. a CPU doesn't have full
> access to task's page tables.. that said, if a TLB miss takes place
> (or some analogue lookup mechanism), the CPU needs assistance from the
> OS and e.g. rises an exception.

Yes.

> [*] A corresponding OS handler gets a 'fault address' and looks for it
> in the task's 'page tables' .. and if found, updates TLB accordingly.

Yes. High-end PowerPC processors have better hw support for virtual to 
physical address translation than low-end processors. They usually just 
have 64 TLB entries or even less (like the MPC 8xx).

> This would be similar to what happens in MIPS :
> TLB miss --> TLB-miss exception --> OS-dependent TLB-miss handler.

Yes.

> Now, Xenomai is not able (at the moment) to do [*] on its own.. thus,
> there is a switch to the secondary mode so that Linux is able to take
> care of it.

But normal TLB misses happen frequently and do not force a switch to 
secondary mode. I think the problem is with the do_page_fault trap. Can 
somebody confirm that?

> Unless there is a way to reserve a set of TLB entries for a real-time
> task (or other mechanism to have 'virtual -> physical' conversion
> entirely in the CPU -- I mean, not involving the OS) + the working set
> of the rt task fits into this 'reserved' set --- 'TLB-miss' exception
> gonna happen.. e.g. every time after the RT relinquish a CPU and
> something else trashes the TLB tables.
> 
> e.g. on MIPS, the area used for kernel modules also requires
> virtual->physical translation.. so even a kernel-mode task (and
> actually, interrupt handlers inside the kernel modules) cause TLB-miss
> exceptions. Sure, it's not a case if it's linked against the kernel
> itself.

Even kernel code may cause a TLB miss. TLB pinning has been abandoned on 
some PowerPC archs because it does reduce overall system performance.

> errr.. ok, to many words :-) does it sound like smth taking place
> here? A link to the MMU overview for ppc would be highly appreciated
> as well.


See above. Unfortunately, I do only a limited, global view of the MMU 
implementation for PowerPC.

Wolfgang.