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From: Jeff Garzik <jeff@garzik.org>
To: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: linux-ide@vger.kernel.org, alan@lxorguk.ukuu.org.uk, rah@bash.sh
Subject: Re: [PATCH 1/2] pata_hpt37x: actually clock HPT374 with 50 MHz DPLL (take 2)
Date: Wed, 15 Aug 2007 04:19:36 -0400	[thread overview]
Message-ID: <46C2B718.8030106@garzik.org> (raw)
In-Reply-To: <200708102058.46160.sshtylyov@ru.mvista.com>

Sergei Shtylyov wrote:
> The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask
> including mode 5 used to check for the necessity of 66 MHz clocking -- this
> caused 66 MHz clock to be used for HPT374 chip that does not tolerate it.
> While fixing this, also remove PLL mode from the TODO list -- I don't think
> it's still a relevant item.
> 
> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
> 
> ---
> This is against the current Linus tree -- with wording in the header fixed. :-)
> 
>  drivers/ata/pata_hpt37x.c |   12 ++++--------
>  1 files changed, 4 insertions(+), 8 deletions(-)

applied 1-2 to #upstream-fixes



      reply	other threads:[~2007-08-15  8:19 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-08-10 16:58 [PATCH 1/2] pata_hpt37x: actually clock HPT374 with 50 MHz DPLL (take 2) Sergei Shtylyov
2007-08-15  8:19 ` Jeff Garzik [this message]

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