From: Fabrice Bellard <fabrice@bellard.org>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH][MIPS] Fix [ls][wd][lr] instructions
Date: Wed, 26 Sep 2007 11:52:33 +0200 [thread overview]
Message-ID: <46FA2BE1.3070307@bellard.org> (raw)
In-Reply-To: <20070926092330.GA29659@hall.aurel32.net>
Aurelien Jarno wrote:
> Hi,
>
> As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr,
> sdl and sdr instructions are not correctly implemented. In case of
> exception the BadVAddr register gets the aligned address instead of the
> unaligned original address.
>
> In addition to that, the store instructions are generating the wrong
> exception, AdEl instead of AdEs, because the current implementation
> first do a load.
>
> The patch below fixes that by accessing the bytes one by one, starting
> by the unaligned original address.
> [...]
It would be a lot more efficient to add specific code in the MIPS
exception handling.
Fabrice.
next prev parent reply other threads:[~2007-09-26 9:52 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-26 9:23 [Qemu-devel] [PATCH][MIPS] Fix [ls][wd][lr] instructions Aurelien Jarno
2007-09-26 9:47 ` Fabrice Bellard
2007-09-26 10:45 ` Aurelien Jarno
2007-09-26 9:52 ` Fabrice Bellard [this message]
2007-09-26 10:45 ` Aurelien Jarno
2007-10-06 11:19 ` Aurelien Jarno
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